3D stacking and through-silicon vias (TSV): Question bank

6.5.3 · D5 · Hardware › Advanced & Emerging Architectures › 3D stacking aur through-silicon vias (TSV)

Recall TSV actually kya hota hai (shuru karne se pehle ek-line refresher)

Ek Through-Silicon Via ek copper-filled tunnel hai jo ek die ke transistor-bearing silicon body ke through drill kiya jaata hai, oxide se line kiya taaki substrate se short na ho, aur us die ko uske upar ya neeche stacked die se connect karta hai.

Definition Is page par use kiye gaye har symbol ki definition — ek baar, pehle se

Neeche ke trap questions teen formulas par lean karte hain. Inhe touch karne se pehle, har letter ko clearly samjho ki woh kya hai aur uski units kya hain. Yeh list padhte waqt cross-section figure dekho.

$a$ ::= TSV ke copper core ka inner radius (metres). Woh metal jo actually signal carry karta hai.
$b$ ::= oxide liner ka outer radius (metres), yaani via centre se us jagah tak ki doori jahan grounded silicon shuru hota hai. Toh $b - a$ liner thickness hai.
$ε$ ::= oxide liner ki absolute permittivity (farads per metre, F/m), $ε = ε_{r} ε_{0}$ . Yeh measure karta hai ki insulator kitna charge store karta hai per volt.
$h$ ::= silicon ke through via ki height (length) (metres) — wafer thickness se set hoti hai.
$ℓ$ ::= signal wire ki length (metres). Horizontal route ke liye $ℓ \sim$ mm; vertical TSV ke liye $ℓ = h \sim 50 μ m$ .
$Q$ ::= stack mein dump ki gayi heat power (watts, W).
$t$ ::= stack ki thickness jiske through heat conduct honi chahiye (metres).
$k$ ::= material ki thermal conductivity (watts per metre-kelvin, W/(m·K)).
$A$ ::= cross-sectional area jiske through heat flow hoti hai (square metres, m²).
$Δ T$ ::= buried hotspot ka temperature rise (kelvin, K).

Figure — 3D stacking and through-silicon vias (TSV)

Formula Teen laws jinhe yeh traps test karte hain (har dependence ka

kyun ke saath) 1 · TSV capacitance (coax model). Copper core, oxide, aur grounded silicon teen concentric cylinders hain — exactly ek coaxial capacitor. Figure mein sketch karo: field lines core se radially nikalti hain, oxide cross karti hain, aur silicon par land karti hain. $C_{TSV} = \frac{2 π ε h}{l n ( b / a )}$ $ln (b / a)$ kyun? Ek line charge ka radial field $E (r) = \frac{λ}{2 π ε r}$ hota hai — bahar jaate waqt yeh $1/ r$ ki tarah weak hota hai. Us field ko $a$ se $b$ tak integrate karke voltage nikalna $\int_{a}^{b} \frac{d r}{r} = ln (b / a)$ deta hai. Logarithm simply ek cylinder ke upar $1/ r$ field ka fingerprint hai; bada $b / a$ (thicker oxide) matlab hai charge per more voltage, isliye kam capacitance. Full derivation parent note 3D stacking and through-silicon vias (TSV) mein hai. 2 · Wire delay law. $τ \propto R C \propto ℓ^{2}$ . $R \propto ℓ$ aur $C \propto ℓ$ kyun? Fixed cross-section ki wire ki resistance uski length ke proportional hoti hai (longer resistor = zyada ohms) aur capacitance bhi length ke proportional hoti hai (wire ke along uniform capacitance-per-unit-length). Dono length-proportional terms multiply karo toh delay $ℓ^{2}$ ki tarah badhta hai. 3 · Fourier heat law. $Δ T = \frac{Q t}{k A}$ . Hotspot ka temperature rise power $Q$ ke saath aur thickness $t$ ke saath badhta hai jiske through heat push honi hai, aur better conductivity $k$ aur wider flow area $A$ ke saath ghatta hai. Yeh lumped form assume karta hai ki heat directly neeche ek fixed area $A$ se flow karta hai — yeh ek broad, uniform layer ke liye achha picture hai.

True or false — justify

Har "true/false" answer neeche verdict aur reason dono deta hai — sirf T/F kuch nahi kamaata.

TSV ki capacitance substrate ke saath kam ho jaati hai agar oxide liner ko thicker banao.

True — thicker oxide matlab larger outer radius

b

, aur

C = \frac{2 π ε h}{l n ( b / a )}

shrink hoti hai jab

ln (b / a)

badhta hai; smaller cap matlab faster, lower-energy signalling.

Wafer thinning mainly isliye help karta hai kyunki chip halki ho jaati hai.

False — thinning via height

h

ko shrink karta hai, aur

C \propto h

hone se shorter via ki capacitance kam hoti hai (aur tip bonding ke liye expose hoti hai). Weight irrelevant hai.

2D chip par wire delay, wire length ke saath linearly scale karta hai.

False — kyunki resistance

R \propto ℓ

aur capacitance

C \propto ℓ

dono hain, delay

τ \propto R C \propto ℓ^{2}

hai; yeh length ke square ke saath badhta hai, yahi wajah hai ki short vertical hops win karte hain.

3D stack 2D chip se zyada I/O deta hai kyunki yeh sirf edge ki jagah poora face use karta hai.

True — 2D I/O perimeter se nikalti hai (

N_{2 D} \propto L

), jabki TSVs poora area cover karte hain (

N_{3 D} \propto L^{2}

); 10 mm die par 40 µm pitch ke saath yeh ~1000 vs ~62,500 links hain.

2.5D integration compute dies ke through TSVs daalta hai.

False — 2.5D mein TSVs interposer ke andar hote hain neeche; compute dies uske upar side by side baithe hain aur unhe drill nahi kiya jaata. Sirf true 3D compute dies ke through drill karta hai.

Zyada stacked layers add karne se achievable performance hamesha badhti hai.

False — shorter wires help karte hain, lekin total power same footprint mein land hoti hai, toh

Δ T = Qt / (k A)

badhta hai aur clocks throttle karne padte hain, jo speedup ko erase kar sakta hai. Ceiling wiring nahi, heat set karti hai.

Oxide liner aur diffusion barrier ek hi kaam karte hain.

False — oxide copper ko semiconducting silicon se electrically insulate karta hai (shorting rokta hai); barrier (jaise TaN) copper atoms ko silicon mein diffuse hone se chemically block karta hai jo transistors ko poison kar sakte hain. Dono alag failures hain.

TSV essentially wiring layers ke beech ek normal metal via jaisi cheez hai.

False — ordinary via interconnect stack ke andar metal layers ko nanometre scale par connect karta hai; TSV silicon substrate ke through micron scale par jaata hai (~1000× bada), jisme oxide liner, wafer thinning, aur keep-out zone chahiye.

Memory-on-logic 3D stacking thermally logic-on-logic se easier hai.

True — memory dies logic se kaafi kam power per area dissipate karte hain, isliye unhe stack karne se shared footprint mein thodi heat add hoti hai; do hot logic dies

Q

compound kar dete aur

Δ T

bahut badh jaata.

HBM TB/s bandwidth mainly isliye achieve karta hai kyunki har wire bahut fast clock hoti hai.

False — yeh bahut wide bus use karta hai (jaise 1024 bits) sirf moderate per-pin rates par; width affordable hai exactly isliye kyunki TSVs area-scaled I/O dete hain, kisi single lane ki heroics ki wajah se nahi.

Spot the error

Har prompt mein ek planted mistake hai; answer usse naam deta hai aur correct karta hai.

"Hum via drill karte hain, copper se fill karte hain, aur ho gaya — wall ko line karne ki zaroorat nahi."

Error: oxide liner skip karta hai. Silicon itna conduct karta hai ki copper substrate se short ho jaaye; insulating liner (aur barrier) ke bina TSV electrically fail hogi aur copper nearby transistors ko poison kar dega.

"TSV capacitance kam karne ke liye hume ek higher permittivity wala oxide use karna chahiye."

Error:

C \propto ε

, isliye higher permittivity liner zyada capacitance deta hai. Tum low-

ε

(low-k) liner chahte ho load reduce karne ke liye.

"Longer TSVs better hote hain kyunki zyada length matlab zyada metal aur lower resistance."

Error: length capacitance badhati hai (

C \propto h

) aur coax cap yahan dominant penalty hai; isliye hum via ko shorten karne ke liye wafer thin karte hain, lengthen nahi karte.

"Kyunki vertical hops ~50 µm hain aur horizontal routes ~5 mm, delay approximately 100× improve hota hai."

Error: delay length squared se scale karta hai, isliye ratio

(50/5000)^{2} = 1 0^{- 4}

hai — lagbhag 10,000× improvement, 100× nahi.

"2.5D aur 3D dono dies ek doosre ke upar stack karte hain, bas inke alag naam hain."

Error: 2.5D dies ko interposer par side by side rakhta hai (TSVs interposer mein hote hain); sirf 3D dies ko directly ek doosre ke upar stack karta hai with TSVs dies ke through.

"Keep-out zone isliye exist karta hai kyunki TSV ko apni electrical field ke liye jagah chahiye."

Error: keep-out zone ek mechanical-stress exclusion hai — copper aur silicon alag expand karte hain, aur resulting stress transistor behaviour shift kar deta, isliye via ke bilkul paas koi active devices nahi hote.

"Bandwidth = bus width, toh ek 1024-bit HBM bus 1024 bytes per second deta hai."

Error: bandwidth = width × per-pin rate, aur bytes ke liye bits ko 8 se divide karna padta hai. 3.2 Gbps/pin par yeh ~410 GB/s per stack hai, 1024 B/s nahi.

Why questions

Data TSV ke through vertically kyun travel karna chahta hai instead of die ke across horizontally?

Kyunki wire delay

\propto ℓ^{2}

hai (

ℓ

wire length): ek 50 µm vertical hop ek millimetres-long horizontal route replace karta hai, same signal ke liye delay aur switching energy orders of magnitude cut karta hai.

3D stacking ek purane saste process ko ek naye mehnge ke saath mix kyun kar sakta hai?

Har die alag se fabricate hoti hai aur baad mein join hoti hai, isliye tum memory/analog ko ek mature low-cost node par aur logic ko leading node par rakh sakte ho — "har layer ke liye sahi tool" (heterogeneous integration).

TSV ek ideal wire ki jagah coaxial capacitor ki tarah behave kyun karta hai?

Copper core (

a

), oxide liner (

b

tak), aur grounded silicon concentric conductors/dielectric form karte hain — exactly ek coax geometry — isliye core par charge substrate ke liye ek cap induce karta hai jo signal ko load aur slow karta hai.

Capacitance simply

(b - a)

par nahi balki

ln (b / a)

par depend kyun karta hai?

Ek line charge ka radial field

1/ r

ki tarah fall off karta hai, isliye oxide ke across use sum karna

1/ r

integrate karta hai, jo logarithm deta hai;

b / a

ke ratio ka log cylindrical geometry ka natural fingerprint hai, plain gap width nahi.

2D chips jab bade hote hain toh I/O khatam kyun ho jaata hai jabki 3D chips better scale karte hain?

2D links edge se nikalte hain, jo sirf perimeter

L

ki tarah badhti hai, jabki TSV links poora face cover karte hain, area

L^{2}

ki tarah badhte hain — toh

L

badhne par face I/O edge I/O se aage nikal jaata hai.

Heat aggressive 3D stacking ke liye true limiting wall kyun hai?

Stacking zyada power

Q

same footprint mein daal deta hai, aur

Δ T = Qt / (k A)

se temperature rise conducting thickness

t

ke saath badhta hai, clock throttling force karta hai jo wiring gains cancel kar deta hai.

TSV ko wafer thinning kyun chahiye jo ek ordinary metal via ko kabhi nahi chahiye?

TSV ko poori silicon body ke through jaana hota hai aur bonding ke liye uska tip expose ("via reveal") karna hota hai; ordinary via thin interconnect stack ke andar rehta hai aur substrate kabhi traverse nahi karta.

Edge cases

TSV capacitance formula ka kya hoga agar oxide vanishingly thin ho jaaye (

b \to a

ln (b / a) \to 0

, toh

C \to \infty

— ek physically-degenerate case matlab copper essentially silicon se touch kar raha hai, yaani koi insulation nahi aur effectively ek short. Yeh liner failure signal karta hai.

Agar tum wafer ko zero height tak thin karo (

h \to 0

), model kya predict karta hai, aur kya yeh realistic hai?

C = \frac{2 π ε h}{l n ( b / a )} \to 0

, toh capacitance khatam ho jaati hai; lekin ek floor hai — tum mechanical/structural limits se neeche thin nahi kar sakte, aur dusre parasitics aur bond joint dominate karte hain, isliye real caps tens of fF mein plateau karte hain.

Ek 3D stack ke liye jiske active layers almost no power dissipate karte hain (jaise sab low-power memory), heat ki jagah performance kya limit karta hai?

Thermal

Δ T

tiny ho jaata hai, toh limit I/O aur interconnect par shift ho jaati hai: TSV pitch, bond yield, aur available bandwidth — woh achha regime jo memory-on-logic (HBM) ko practical banata hai.

Kya hoga agar die ki saari power ek single tiny hotspot se aaye instead of spread out hone ke?

Lumped

Δ T = Qt / (k A)

assume karta hai ki heat directly neeche fixed area

A

se flow karta hai; ek point source instead sideways spread karta hai, isliye true model ko spreading resistance chahiye aur effective

A

depth ke saath badhta hai — simple formula

Δ T

over-predict karta hai agar tum naively hotspot area plug in karo, aur under-predict karta hai agar tum poori die use karo. Ise sirf wahan use karo jahan heat source roughly

A

fill kare.

Jab pad/TSV pitch

p

zero ki taraf shrink ho,

N_{3 D} = L^{2} / p^{2}

I/O count practice mein kya cap karta hai?

Manufacturing aur stress limits: sub-micron pitch bonding alignment, keep-out-zone overlap, aur yield loss mein run karta hai, isliye

1/ p^{2}

growth

p \to 0

se bahut pehle saturate ho jaati hai.

N_{3 D} \propto L^{2}

N_{2 D} \propto L

comparison ek bahut chote die ke liye kya predict karta hai jahan

L

sirf kuch pad-pitches wide ho?

Advantage almost khatam ho jaata hai — chote

L

ke liye face mein few TSVs hote hain aur edge I/O comparable hota hai, isliye 3D ka area benefit tabhi payoff karta hai jab die itni badi ho ki many face connections ho sakein.

Recall Exam se pehle sabse fast self-check

Delay law? ::: $τ \propto R C \propto ℓ^{2}$ ( $ℓ$ = wire length) — squared, isliye short hops bade win karte hain. I/O scaling 2D vs 3D? ::: perimeter $L$ vs area $L^{2}$ . Real 3D ceiling? ::: heat, via $Δ T = Qt / (k A)$ . 2.5D vs 3D ek word mein? ::: beside (interposer) vs atop (through-die).

Yeh bhi dekho: High Bandwidth Memory (HBM) · Interposers and 2.5D Integration · Interconnect RC Delay · Chiplets and Heterogeneous Integration · Thermal Management in ICs · Chip Packaging