3D stacking and through-silicon vias (TSV): Visual walkthrough

6.5.3 · D2 · Hardware › Advanced & Emerging Architectures › 3D stacking and through-silicon vias (TSV)

Step 0 — Hum jo object measure kar rahe hain, woh hai kya?

KYA kiya humne: parts ko naam diya. KYU: formula tab tak sense nahi karta jab tak tum drawing par $a$ , $b$ , $h$ point nahi kar sakte. KAISA DIKHTA HAI: figure s01 — copper (amber) core, cyan oxide ring, blueprint silicon uske around.

Step 1 — Wire par charge daalo, poochho ki woh kaunsa field banata hai

KYU yeh tool (field): voltage yahan directly likha nahi ja sakta — gap curved hai, flat plates nahi hain. Lekin voltage sirf field ko ek path ke saath add up karna hai. Toh $V$ paane ke liye, pehle $E$ paana padega. Field stepping stone hai.

KAISA DIKHTA HAI: figure s02 — cyan field arrows copper line se seedhe bahar shoot karte hue, core ke paas longer (stronger), door shorter.

Step 2 — Gauss's law field ki exact shape deta hai

Copper ke around radius $r$ aur length $h$ ka ek imaginary cylinder wrap karo (figure s03). Field har jagah iske curved side par same strength ka hai (symmetry), aur us side ka area $2 π r h$ hai (circumference $2 π r$ times height $h$ ). Trapped charge $λh$ hai. Toh:

$radius r par field E (r) \times area jisme se field poke karta hai 2 π r h = trapped charge / ε \frac{λh}{ε}$

$h$ cancel karo, $E$ ke liye solve karo:

$E (r) = \frac{λ}{2 π ε r}$

$λ$ — charge per length: zyada charge, zyada strong field.
$r$ — centre se distance: field $1/ r$ ki tarah fade hota hai jaise tum bahar jaate ho. Yahi key shape hai.
$2 π$ — circle ki circumference se aata hai; yeh geometry hai, physics nahi.
$ε$ — oxide kitna field "soak up" karta hai (Step 3).

KYA kiya humne: symmetry use karke $E (r)$ exactly nail kiya. KYU: ab hamare paas voltage ka stepping stone hai. KAISA DIKHTA HAI: figure s03 — dashed Gaussian cylinder, arrows iske side ke around sab equal.

Step 3 — $ε$ kya hai, aur oxide ka version kyun matter karta hai

KYU yeh yahan aata hai: Step 2 ka field oxide liner ke andar rehta hai ( $a$ aur $b$ ke beech), isliye hum jo $ε$ use karte hain woh oxide ki permittivity hai. Yahi jagah hai jahan material choice formula mein ghusta hai — aur isliye engineers low- $ε$ liners dhundte hain: woh $C$ kam karte hain.

KAISA DIKHTA HAI: figure s04 — wahi field arrows oxide vs vacuum se fill hone par shrink hote hue, $ε$ "softening" the field dikhate hue.

Step 4 — Voltage paane ke liye ek path pe field add karo

$V = \int_{a}^{b} E (r) d r = \int_{a}^{b} \frac{λ}{2 π ε r} d r$

$\int_{a}^{b} \dots d r$ — "field ko $a$ se $b$ tak har sliver ke upar add karo."
Andar sirf $\frac{1}{r}$ change ho raha hai.

$\frac{1}{r}$ ka integral natural logarithm $ln$ hai. ( $ln$ kyun? Kyunki $ln$ define hi aise kiya gaya hai ki $1/ r$ ke neeche running area — yeh exactly " $1/ r$ sum up karne" ka answer hai. Koi doosra function yeh nahi karta.) Toh:

$V = \frac{λ}{2 π ε} [ln r]_{a}^{b} = \frac{λ}{2 π ε} ln \frac{b}{a}$

$ln \frac{b}{a}$ — geometry factor: yeh sirf do radii ke ratio ki parwah karta hai, unke absolute size ki nahi. Moti liner (bada $b$ ) → bada $ln (b / a)$ → same charge ke liye bada voltage.

KYA kiya humne: liner ke across integrate karke field ko voltage mein convert kiya. KYU: $C = Q / V$ ko $V$ chahiye, aur ab hamare paas hai. KAISA DIKHTA HAI: figure s05 — $1/ r$ curve jisme $a$ se $b$ tak shaded area "yeh area = voltage = $ln (b / a)$ " label kiya gaya hai.

Step 5 — Divide karo: charge over voltage se capacitance milta hai

Ab $C = Q / V$ assemble karo. Yaad karo $Q = λh$ (charge per length times height):

$C = \frac{Q}{V} = \frac{λh}{\frac{λ}{2 π ε} l n \frac{b}{a}}$

$λ$ upar aur neeche cancel ho jaata hai (capacitance kabhi depend nahi karta ki kitna charge tum daalo — yahi poora point hai ki yeh geometry ki ek fixed property hai). Divided fraction flip karke:

$C_{TSV} = \frac{2 π ε h}{ln ( b / a )}$

KAISA DIKHTA HAI: figure s06 — finished cross-section jisme har symbol us part se pin kiya gaya hai jise woh control karta hai, plus arrows "↑h ⇒ ↑C" aur "↑liner ⇒ ↓C."

Step 6 — Edge aur degenerate cases (kabhi gap mat chhodna)

Intuition Formula ko uske limits tak push karo

Jis formula par tumhara trust ho, woh extremes mein survive karna chahiye. Figure s07 dekho.

Bahut patli liner, $b \to a$ : toh $b / a \to 1$ aur $ln (1) = 0$ , isliye $C \to \infty$ . Sahi — vanishingly thin insulator near short hai; do conductors almost touch karte hain aur enormous charge store karte hain. Physically yeh woh failure mode hai jahan TSV substrate mein leak karta hai.
Bahut moti liner, $b ≫ a$ : $ln (b / a)$ bada ho jaata hai, $C \to 0$ . Yeh bhi sahi hai — wall ko door khींcho aur almost koi coupling nahi hogi. Lekin fat liner precious area chura leta hai, isliye real designs ek modest ratio choose karte hain (e.g. $a = 2.5 μ m$ , $b = 3 μ m$ ).
Zero height, $h \to 0$ (infinitely thin die): $C \to 0$ . Bina length ke via ka koi wall area nahi hai couple karne ke liye. Yahi ideal hai jise hum thinning se chase karte hain — chhota $h$ , chhota $C$ .
$a = 0$ (koi copper nahi): $ln (b /0) = ln (\infty) = \infty$ , isliye $C \to 0$ — koi conductor nahi toh charge karne ke liye kuch nahi. Sanity bani rehti hai.

Ek-picture summary

Figure s08 poori chain ko ek flow mein stitch karta hai: copper par charge → Gauss deta hai $E = λ /2 π ε r$ → liner ke across integrate karna deta hai $V = \frac{λ}{2 π ε} ln \frac{b}{a}$ → $Q / V$ divide karna deta hai $C = \frac{2 π ε h}{l n ( b / a )}$ , result se design levers ( $h$ , liner thickness, $ε$ ) hanging hote hue.

Recall Feynman retelling — plain words mein wapas bolo

Ek TSV ek copper straw hai jo ek chip ke through push ki gayi hai, ek patli insulating sleeve mein wrap ki hui, aur chip ka silicon body bahar wall ki tarah hai. Copper aur silicon do conductors hain jisme beech mein insulator hai — yeh capacitor hai, aur capacitor signals slow karta hai aur energy burn karta hai, isliye hum chahte hain ki iska number chhota ho. Woh number dhundhne ke liye maine pucha "charge per volt kitna?" Maine copper par charge daala, aur kyunki shape perfect cylinder hai isliye maine Gauss's law use karke turant field paaya: woh outward point karta hai aur $1/ r$ ki tarah kamzor hota hai. Us field ko voltage mein convert karne ke liye maine use insulating sleeve ke across add up kiya — $1/ r$ add karne se logarithm milta hai, isliye voltage mein $ln (b / a)$ aata hai, jahan $a$ copper ka radius hai aur $b$ sleeve ka baahri hissa hai. Charge ko voltage se divide karne par, charge amount cancel ho jaata hai (capacitance pure geometry hai), aur bachta hai $C = \frac{2 π ε h}{l n ( b / a )}$ . Ise padhna: zyada tall via ( $h$ ) ka matlab zyada $C$ hai (bura) — isliye hum wafer grind karke thin karte hain. Moti sleeve ya lower-permittivity material ka matlab kam $C$ hai (achha). Aur extremes theek behave karte hain: touching conductors infinite $C$ dete hain, door wall ya zero height zero $C$ deta hai. Yahi poora result hai, honestly earned.

Recall Quick self-test

Wafer thin karne se TSV capacitance kyun kam hoti hai? ::: $C \propto h$ ; kam height $h$ ka matlab hai copper se silicon ko kam wall area couple karta hai, isliye directly kam $C$ . Formula mein logarithm kyun hai? ::: Voltage field ka liner ke across integral hai, aur field $1/ r$ ki tarah jaata hai; $1/ r$ ka integral $ln$ hai, $a$ se $b$ tak evaluate karne par $ln (b / a)$ milta hai. $ε$ physically kya represent karta hai aur ise low kyun prefer karte hain? ::: Liner ki permittivity — woh kitni aasaani se field store karta hai; low- $ε$ liners kam charge store karte hain, lower $C$ dete hain, faster aur lower-energy signals.

Yeh bhi dekho: Interconnect RC Delay (kyun $C$ time aur energy cost karta hai), High Bandwidth Memory (HBM) aur Interposers and 2.5D Integration (jahan hazaron yeh vias parallel mein chalti hain), Thermal Management in ICs (woh wall jisme yeh sab run karta hai), aur Chiplets and Heterogeneous Integration.