3D stacking and through-silicon vias (TSV): Foundations

6.5.3 · D1 · Hardware › Advanced & Emerging Architectures › 3D stacking and through-silicon vias (TSV)

Is page par assume kiya gaya hai ki tumhe kuch nahi pata. parent topic mein use hone wala har letter, ratio, aur squiggle yahan se ground up se build kiya gaya hai, uss order mein jo har ek ko pehle wale par lean karne deta hai.

0. Woh picture jisme poora topic rehta hai

Kisi bhi symbol se pehle, yeh image pakad lo: ek chip silicon ka ek flat square hai jisme tiny switches (transistors) hain aur unhe connect karne wali thin metal wires hain. 3D stacking ek doosre aaise square ko seedha upar rakhti hai, aur unhe connect karne ke liye seedhe neeche tunnels drill karta hai.

Figure — 3D stacking and through-silicon vias (TSV)

Neeche sab kuch woh vocabulary hai jo describe karne ke liye chahiye ki floors ke beech ka elevator kaise kaam karta hai aur elevator kyun jeet ta hai.

1. Length aur hum tiny ko kaise measure karte hain — µm

Powers of ten jo tumhe milenge, smallest (most negative exponent) pehle:

Symbol	Naam	Matlab	Kahan dikhta hai
$f$	femto	$1 0^{- 15}$	capacitance (fF)
$p$	pico	$1 0^{- 12}$	capacitance (pF), delays
$n$	nano	$1 0^{- 9}$	ordinary metal vias, transistor sizes
$μ$	micro	$1 0^{- 6}$	TSV width aur height
$m$	milli	$1 0^{- 3}$	full chip width $L$

Yeh prefixes bas ek number ke aage stickers hain jo batate hain ki kis power of ten se multiply karna hai. Isse zyada mysterious kuch nahi.

2. Multiply karna, divide karna, aur log — growth ki shapes

Parent note baar baar kehta hai koi cheez doosri cheez ki tarah "grow" karti hai. Uss phrase ka matlab hai: agar main ek quantity bada karun, doosra kaise respond karta hai? Teen response-shapes appear hote hain.

Recall Hum yahan care kyun karte hain ki

$ln$ slowly grow karta hai? Kyunki yeh capacitance formula ke denominator mein hai. Slowly-changing denominator ka matlab hai capacitance oxide thickness mein small manufacturing variation ke forgiving hai. ::: Slow-growing denominator → stable, predictable capacitance.

3. Charge, voltage, current — electrical alphabet

Physics derivations mein har symbol chaar everyday electrical ideas se aata hai. Pipes mein paani ki picture banao.

4. Capacitance $C$ — poore topic ka star

Neeche ki figure is definition ko do water tanks ke roop mein draw karti hai — narrow tank (chhota $C$ , thode charge se bhar jaata hai) versus wide tank (bada $C$ , same rise ke liye charge peeta hai). Continue karne se pehle isko left-to-right padho; baad ka har "big tank / tiny tank" phrase is picture par point karta hai.

Formula Geometry + permittivity se TSV capacitance formula build karna

KYU: parent note baar baar $C_{TSV}$ quote karta rehta hai, aur D1 ne promise kiya tha ki build karega. Yahan hai, teen nested cylinders (core radius $a$ , oxide out to $b$ , height $h$ ) aur §6 se material knob $ε$ se. Core par unit length ke hisaab se charge $λ$ ek electric field banata hai jo (Gauss's law se) $r$ distance par $E_{field} (r) = \frac{λ}{2 π ε r}$ ki tarah fall off karta hai. Core se oxide edge tak field-slope ko add karna (integrating) oxide ke across voltage deta hai: $V = \int_{a}^{b} E_{field} d r = \frac{λ}{2 π ε} ln \frac{b}{a} .$ Kyunki $C = Q / V$ aur total charge $Q = λh$ hai, $λ$ cancel ho jaata hai aur bachta hai $C_{TSV} = \frac{2 π ε h}{ln ( b / a )}$ Padho: thicker oxide (bada $b / a$ ) → denominator mein bada $ln$ → chhota $C$ → faster, lower-energy tunnel. Taller via (bada $h$ ) → bada $C$ — yahi exact reason hai wafer ko thin kiya jaata hai taaki $h$ shrink ho sake.

5. Resistance $R$ aur RC product — jahan delay janam leta hai

Recall Agar ek wire ki length triple ho jaaye, toh uska RC delay kitna badlega?

$\times 9$ . ::: Kyunki delay $\propto ℓ^{2}$ aur $3^{2} = 9$ .

6. Tunnel ke geometry symbols — $a$ , $b$ , $h$ , $L$ , $p$

TSV ko teen nested cylinders ke roop mein model kiya jaata hai. Unke radii naam karne se formulas exact ban jaate hain.

7. Perimeter vs area — kyun $L$ vs $L^{2}$ bandwidth story hai

8. Heat: $Q_{heat}$ , $k$ , $A$ , $t$ , $Δ T$ — woh villain jo infinite stacking rokta hai

Prerequisite map

Har foundation box topic ko exactly wahan feed karta hai jahan parent note ise use karta hai: growth-shapes + $R$ + $C$ delay argument banate hain, geometry + permittivity capacitance formula banate hain, perimeter-vs-area bandwidth argument banata hai, aur heat woh counterweight hai jo sab ko limit karta hai.

Delay story Interconnect RC Delay mein continue hoti hai; "wires shrinking kyun ruk gaye" backstory Moore's Law hai; stacking ka side-by-side cousin Interposers and 2.5D Integration hai; alag processes ke dies mix karna Chiplets and Heterogeneous Integration hai; heat wall Thermal Management in ICs mein detail mein hai; aur yeh sab ek product mein kaise seal hota hai Chip Packaging hai.

Equipment checklist

Self-test: kya tum reveal karne se pehle har ek aloud bol sakte ho?

"::=" sign ko kaise padhein

"is defined as" — left side naya word hai, right side uska plain-words meaning.

1 μ m

metres mein

1 0^{- 6} m

(ek metre ka ek millionth).

Letter "m" ke do matlab

prefix milli (

1 0^{- 3}

) jab kisi unit ke aage ho; akele khada ho toh unit metre.

y \propto x^{2}

ka matlab

x

double karne par

y

4× bada ho jaata hai.

ln

TSV formula mein kyun appear karta hai aur hum uski exact value kyun nahi sochte

yeh bahut slowly grow karta hai, isliye capacitance oxide-ratio variation ke forgiving hai.

Ek sentence mein capacitance

voltage rise ke per volt charge chahiye,

C = Q / V

; "tank ki cross-section."

E_{field}

aur

E

mein fark

E_{field}

electric field hai (direction wala slope); akela

E

energy hai (joules ki ek number).

Ek capacitor switch karne ki energy

E = \frac{1}{2} C V^{2}

;

\frac{1}{2}

average back-pressure discount hai.

TSV capacitance formula

C_{TSV} = \frac{2 π ε h}{ln ( b / a )}

— radii

a

b

aur height

h

ke nested cylinders se.

Wire delay length squared ki tarah kyun grow karta hai

dono

R \propto ℓ

aur

C \propto ℓ

hain, aur

τ = R C \propto ℓ^{2}

TSV par

a

b

h

kya hain

copper-core radius, oxide-edge radius, tunnel height.

Radii ratio

b / a

ke roop mein kyun aate hain

coaxial physics sirf proportion par depend karta hai, absolute size par nahi.

Words mein permittivity

ε

ek insulator electric field ko kitni aasaani se pass karta hai;

C

ke liye material knob.

Perimeter vs area scaling

edge

\propto L

(kam links), face

\propto L^{2}

(zyada links) → bandwidth win.

Fourier temperature rise

Δ T = Q_{heat} t / (k A)

; thicker/hotter stacks aur hot hote hain → stacking limit.