3D stacking and through-silicon vias (TSV): Worked examples

6.5.3 · D3 · Hardware › Advanced & Emerging Architectures › 3D stacking and through-silicon vias (TSV)

Koi bhi symbol aane se pehle, chalte hain inhe simple words mein samjhte hain taaki koi bhi newcomer pehli line se shuru kar sake.

Definition Woh symbols jo hum use karenge (har ek ek picture se juda hai)

Ek copper ka straw imagine karo jo silicon ke ek slice ke seedha andar ghusa hua hai.

$a$ ::= copper core ka radius (metal filling), metres mein. Yeh straw ka andar wala circle hai.
$b$ ::= oxide liner ke outer edge tak ka radius, copper ke around ek patla glass ka sleeve. Toh $b > a$ hamesha.
$h$ ::= via ki height (length), matlab silicon slice kitni moti hai. Yeh vertical drop hai.
$ε$ ::= oxide ki permittivity — ek material number jo batata hai "yeh insulator per volt kitna charge absorb karta hai." Hum likhte hain $ε = ε_{r} ε_{0}$ , jahan $ε_{0} = 8.85 \times 1 0^{- 12}$ F/m vacuum ki value hai aur $ε_{r}$ (ek pure number) hai jo batata hai vacuum se kitna zyada.
$C$ ::= capacitance farads (F) mein. Ek farad = ek coulomb charge stored per volt. TSVs femtofarads mein aate hain, $1 fF = 1 0^{- 15}$ F.
$V$ ::= signalling voltage (volts) — logic "1" ki height.
$L$ ::= ek square die ki side length; $p$ ::= pitch, connection pads ki centre-to-centre spacing.

Figure dekho: copper core (blue), pale oxide ring (yellow) $b$ tak, aur grey silicon jiske against bahar ka voltage measure hota hai. Neeche ke har formula is ek cross-section se padhte hain.

The scenario matrix

Yeh har case class hai jo yeh topic tumhare saamne rakh sakta hai. Har row ek "cell" hai; aakhri column us example ka naam batata hai jo us pe land karta hai.

#	Case class	Kya push ho raha hai	Example
A	Baseline capacitance	ordinary $a, b, h$	Ex 1
B	Degenerate: thin oxide $b \to a$	$ln (b / a) \to 0$ , limiting behaviour	Ex 2
C	Degenerate: zero length $h \to 0$	$C \to 0$ (the thinning limit)	Ex 3
D	Energy capacitance se	apply $E = \frac{1}{2} C V^{2}$ , compare 2D/3D	Ex 4
E	Sign / direction of change	kaun sa knob help karta hai? sensitivity	Ex 5
F	I/O counting, edge vs area	$N_{2 D}$ vs $N_{3 D}$ , crossover	Ex 6
G	Real-world word problem	HBM bandwidth end-to-end	Ex 7
H	Thermal limiting case	Fourier $Δ T$ , the ceiling	Ex 8
I	Exam twist	oxide thickness ke liye back-solve	Ex 9

Ab hum inhe order mein chalte hain. Har numeric answer page ke neeche machine-checked hai.

Copper core $a = 2.5 μ m$ , oxide out to $b = 3 μ m$ , height $h = 50 μ m$ , oxide $ε_{r} = 3.9$ . Forecast: pehle answer guess karo — kya yeh picofarads (10⁻¹²) mein hoga ya femtofarads (10⁻¹⁵) mein? (Real TSVs tens of fF mein hote hain; aage padhne se pehle guess commit karo.)

Step 1. $ε = ε_{r} ε_{0} = 3.9 \times 8.85 \times 1 0^{- 12} = 3.4515 \times 1 0^{- 11}$ F/m. Yeh step kyun? Formula ko liner ki absolute permittivity chahiye, relative number nahi. Step 2. $ln (b / a) = ln (3/2.5) = ln (1.2) = 0.1823$ . Yeh step kyun? Yeh log coax derivation ka pure-geometry factor hai — yeh measure karta hai ki core aur silicon ke beech kitne "e-foldings" of radius hain. Step 3. $C = \frac{2 π ε h}{ln ( b / a )} = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 50 \times 1 0 ^{- 6} )}{0.1823} = 5.95 \times 1 0^{- 14}$ F. Yeh step kyun? Boxed formula mein direct substitution.

Verify: $5.95 \times 1 0^{- 14}$ F $= 59.5$ fF — tens of femtofarads, "real TSVs are tens of fF" wale sanity note se match karta hai. Units: (F/m)·(m) = F. ✓

Cell B — Degenerate: thin oxide $b \to a$

Worked example Ex 2 — liner vanishingly thin hone par kya hota hai?

$a = 2.5 μ m$ , $h = 50 μ m$ , $ε_{r} = 3.9$ rakho, lekin liner itna shrink karo ki $b = 2.55 μ m$ (sirf $50$ nm oxide). Forecast: kya $C$ Ex 1 se upar jayega ya neeche? Denominator dekho.

Step 1. $ln (b / a) = ln (2.55/2.5) = ln (1.02) = 0.019803$ . Yeh step kyun? Jaise $b \to a$ , ratio $b / a \to 1$ aur $ln (1) = 0$ ; log zero ki taraf collapse ho jaata hai. Step 2. $C = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 50 \times 1 0 ^{- 6} )}{0.019803} = 5.476 \times 1 0^{- 13}$ F $= 547.6$ fF. Yeh step kyun? Same formula; tiny denominator capacitance ko Ex 1 ke mukable ~9× blow up kar deta hai.

Verify (limit reasoning): limit mein $b \to a$ , $ln (b / a) \to 0^{+}$ toh $C = \frac{2 π ε h}{ln ( b / a )} \to + \infty$ . Physically: do conductors ke beech paper-thin insulator ek huge capacitor hota hai — exactly ek parallel-plate capacitor jiske plates almost touch kar rahe hain. Toh degenerate case "no capacitance" nahi balki infinite capacitance hai, signal speed ke liye sabse bura. Isliye liners ko arbitrarily thin nahi banaya ja sakta. ✓

Cell C — Degenerate: zero length $h \to 0$

Worked example Ex 3 — wafer-thinning limit

Same $a = 2.5 μ m$ , $b = 3 μ m$ , $ε_{r} = 3.9$ . Ab poochho: jaise wafer grind karke patla karte hain, $h \to 0$ . $C$ kya karta hai, aur nearly-zero $h = 1 μ m$ par $C$ kya hoga? Forecast: parent note ne kaha tha wafer thinning $C$ shrink karta hai. Toh pehle trend predict karo, phir number.

Step 1. $C = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 1 \times 1 0 ^{- 6} )}{0.1823} = 1.19 \times 1 0^{- 15}$ F $= 1.19$ fF. Yeh step kyun? $C \propto h$ directly, toh $h$ ko 50 µm se 1 µm karna $C$ ko 50× cut kar deta hai. Ex 1 ke 59.5 fF se ≈1.19 fF. ✓ Step 2. Limit lo: jaise $h \to 0$ , $C \to 0$ . Yeh step kyun? Zero length wala via koi via nahi hai — charge store karne ke liye koi cylindrical surface hai hi nahi. Formula is edge par continuous aur well-behaved hai: koi blow-up nahi, cleanly zero ki taraf jaata hai.

Verify: $1.19$ fF, $59.5$ fF ka 1/50 hai rounding ke andar: $59.5/50 = 1.19$ . ✓ Limit $h \to 0 \Rightarrow C \to 0$ physics confirm karta hai: patla wafer = lower load = faster, isliye hum thin karte hain.

Cell D — Energy per switch

Worked example Ex 4 — energy saved per bit (3D vs 2D)

$V = 0.9$ V par signalling. Lamba cross-chip 2D wire $C_{2 D} = 1$ pF $= 1 \times 1 0^{- 12}$ F. Hamaara TSV $C_{3 D} = 60$ fF $= 6 \times 1 0^{- 14}$ F. Forecast: energy-saving ratio guess karo — 2×? 10×? 100×?

Step 1. $E_{2 D} = \frac{1}{2} C_{2 D} V^{2} = \frac{1}{2} (1 \times 1 0^{- 12}) (0.9)^{2} = 4.05 \times 1 0^{- 13}$ J. Yeh step kyun? Jab bhi ek wire flip hoti hai, tum uski capacitance ko $V$ tak charge karte ho; stored energy (jo baad mein heat ke roop mein dump hoti hai) $\frac{1}{2} C V^{2}$ hai. Step 2. $E_{3 D} = \frac{1}{2} (6 \times 1 0^{- 14}) (0.9)^{2} = 2.43 \times 1 0^{- 14}$ J. Yeh step kyun? Same law, tiny TSV capacitance. Step 3. ratio $= E_{2 D} / E_{3 D} = 4.05 \times 1 0^{- 13} /2.43 \times 1 0^{- 14} = 16.67$ . Yeh step kyun? $V^{2}$ cancel ho jaata hai, toh energy ratio sirf capacitance ratio $1000/60 \approx 16.7$ hai.

Verify: $C$ -ratio $1 pF /60 fF = 1000/60 = 16.67$ , energy ratio ke barabar — kyunki $V$ shared hai, energy exactly $C$ track karta hai. Units: F·V² = C·V = J. ✓ ~17× less energy per bit.

Cell E — Sign / direction of change (kaun sa knob help karta hai?)

Worked example Ex 5 — sensitivity: maine oxide thickness double ki,

$C$ ka kya hua? Ex 1 se shuru karo ( $a = 2.5$ , $b = 3$ , toh oxide $0.5 μ m$ thick, $C_{1} = 59.5$ fF). Ab oxide thickness double karo: $b = 3.5 μ m$ (oxide $= 1.0 μ m$ ). Naya $C$ aur uski sign of change nikalo. Forecast: mota insulator — kya $C$ badhega ya ghutega? Roughly kitna?

Step 1. $ln (b / a) = ln (3.5/2.5) = ln (1.4) = 0.3365$ . Yeh step kyun? Bada $b$ ⇒ bada ratio ⇒ bada log ⇒ bada denominator. Step 2. $C_{2} = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 50 \times 1 0 ^{- 6} )}{0.3365} = 3.222 \times 1 0^{- 14}$ F $= 32.2$ fF. Yeh step kyun? Same formula; bada denominator $C$ ko shrink karta hai. Step 3. Change: $C_{2} / C_{1} = 32.2/59.5 = 0.541$ — capacitance 54% tak gir gayi. Yeh step kyun? Parent note ka "thicker oxide → smaller $C$ → faster" confirm karta hai. Note karo yeh exactly half nahi hua — kyunki $C$ oxide thickness par linearly nahi balki $ln (b / a)$ par depend karta hai. Gap double karne se log sirf $0.182$ se $0.336$ (≈1.85×) badhaa, toh $C$ $1/1.85 \approx 0.54$ tak gira.

Verify: $0.1823/0.3365 = 0.5418$ , $C$ -ratio $0.541$ se match karta hai ( $2 π ε h$ prefactor cancel ho jaata hai). ✓ Effect ki sign: negative — mota liner hamesha $C$ ghataata hai, lekin diminishing (logarithmic) returns ke saath.

Cell F — I/O counting, edge vs area

Worked example Ex 6 — perimeter links vs whole-face links

$L = 10$ mm side wala ek square die, pad pitch $p = 40 μ m$ . Edge-only I/O ( $N_{2 D} = 4 L / p$ ) aur full-face TSV I/O ( $N_{3 D} = L^{2} / p^{2}$ ) count karo. Forecast: parent ne kaha tha ~60×. Compute karne se pehle dono counts predict karo.

Step 1. Convert karo: $L = 10000 μ m$ , $p = 40 μ m$ . Yeh step kyun? Divide karne se pehle dono quantities same unit mein honi chahiye. Step 2. $N_{2 D} = 4 L / p = 4 (10000) /40 = 1000$ . Yeh step kyun? Connections sirf 1D perimeter ( $4 L$ of edge) se nikalt hain, $p$ ke spacing par, toh count $L$ mein linearly badhta hai. Step 3. $N_{3 D} = (L / p)^{2} = (10 000/40)^{2} = 25 0^{2} = 62500$ . Yeh step kyun? TSVs 2D face ( $L^{2}$ area) ko $p \times p$ grid par tile karte hain, toh count $L$ mein quadratically badhta hai. Step 4. Ratio $= 62 500/1000 = 62.5$ . Yeh step kyun? Area beats perimeter by $L / (4 p) = 10 000/160 = 62.5$ .

Verify: $N_{3 D} / N_{2 D} = (L^{2} / p^{2}) / (4 L / p) = L / (4 p) = 10 000/ (4 \cdot 40) = 62.5$ . ✓ ~60× zyada parallel links — yahi HBM ki ultra-wide bus ka beej hai.

Cell G — Real-world word problem

Worked example Ex 7 — HBM stack bandwidth, end to end

Ek HBM stack 1024-bit-wide vertical bus (TSVs ke zariye) present karta hai, har pin 3.2 Gbps (gigabits per second) par run karta hai. Ek GPU 4 aise stacks use karta hai. Total bandwidth (TB/s mein) kya deliver hoga? Forecast: single stack ~0.4 TB/s. Char stacks — compute karne se pehle guess karo.

Step 1. Per-stack bit rate $= 1024 \times 3.2 \times 1 0^{9} = 3.2768 \times 1 0^{12}$ bit/s. Yeh step kyun? Bandwidth = bus width (parallel lanes) × per-lane rate. 1024 ki width sirf isliye feasible hai kyunki TSVs area-scaled I/O dete hain. Step 2. bits→bytes convert karo (÷8): $3.2768 \times 1 0^{12} /8 = 4.096 \times 1 0^{11}$ B/s $= 409.6$ GB/s. Yeh step kyun? Data sheets bytes mein quote karte hain; 8 bits = 1 byte. Step 3. Char stacks: $4 \times 409.6 = 1638.4$ GB/s $= 1.6384$ TB/s. Yeh step kyun? Stacks parallel mein operate karte hain, toh bandwidths add hote hain.

Verify: $1024 \times 3.2 \times 1 0^{9} \times 4/8 = 1.6384 \times 1 0^{12}$ B/s $= 1.64$ TB/s. Units: bit/s ÷ (bit/byte) = byte/s. ✓ Ek terabyte per second se zyada — vertical, area-scaled connectivity ka payoff.

Cell H — Thermal limiting case (real ceiling)

Worked example Ex 8 — ek buried logic layer kitna hot hota hai?

Fourier's law of heat conduction: $Q = \frac{k A Δ T}{t} \Rightarrow Δ T = \frac{Qt}{k A}$ , jahan $Q$ heat power (W) hai jo ek slab cross karta hai, $k$ uski thermal conductivity (W/m·K) hai, $A$ area hai, $t$ woh thickness hai jitni heat cross karni hai. Silicon $k = 150$ W/m·K. Ek buried die $Q = 20$ W dissipate karta hai area $A = 1 cm^{2} = 1 \times 1 0^{- 4} m^{2}$ par, aur heat ko $t = 100 μ m$ stacked silicon se guzar kar escape karna hai. Forecast: kuch °C? tens of °C? Solve karne se pehle predict karo.

Step 1. $Δ T = \frac{Qt}{k A} = \frac{( 20 ) ( 100 \times 1 0 ^{- 6} )}{( 150 ) ( 1 \times 1 0 ^{- 4} )}$ . Yeh step kyun? Fourier's law ko temperature rise ke liye solve karo: zyada power ya mota stack → zyada hot; better conductor ya bada area → thanda. Step 2. Numerator $= 20 \times 1 0^{- 4} = 2 \times 1 0^{- 3}$ ; denominator $= 150 \times 1 0^{- 4} = 1.5 \times 1 0^{- 2}$ . Yeh step kyun? Numerator aur denominator alag rakhna slip se bachata hai. Step 3. $Δ T = 2 \times 1 0^{- 3} /1.5 \times 1 0^{- 2} = 0.133$ K single buried layer ke liye. Yeh step kyun? Per layer kam — lekin $Δ T \propto Q t$ : layers double karo ⇒ roughly $Q$ aur $t$ dono double ⇒ ~4× rise, aur hotspots (small $A$ ) ise bahut worse banate hain. Yahi woh wall hai jo logic-on-logic stacking ko cap karti hai.

Verify: $Δ T = 2 \times 1 0^{- 3} /1.5 \times 1 0^{- 2} = 0.1333$ K. Units: (W·m)/((W/m·K)·m²) = K. ✓ Thermal Management in ICs dekho ki yeh scaling kyun memory-on-logic pairing force karta hai.

Cell I — Exam twist (back-solve)

Worked example Ex 9 — "Liner design karo": target hit karne ke liye

$b$ solve karo Ek exam tumhe TSV budget deta hai: $C \leq 40$ fF rakhna hai. Given $a = 2.5 μ m$ , $h = 50 μ m$ , $ε_{r} = 3.9$ , minimum oxide outer radius $b$ nikalo (hence minimum liner thickness). Forecast: Ex 1 ( $b = 3$ par 60 fF) aur Ex 5 ( $b = 3.5$ par 32 fF) se, answer $b = 3$ aur $b = 3.5 μ m$ ke beech hona chahiye.

Step 1. Formula ko log ke liye rearrange karo: $ln (b / a) = \frac{2 π ε h}{C}$ . Yeh step kyun? $b$ ek logarithm ke andar trapped hai, toh pehle $ln (b / a)$ isolate karo, phir log undo karo. Step 2. $ln (b / a) = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 50 \times 1 0 ^{- 6} )}{40 \times 1 0 ^{- 15}} = \frac{1.0844 \times 1 0 ^{- 14}}{4 \times 1 0 ^{- 14}} = 0.2711$ . Yeh step kyun? Target $C = 40$ fF isolated form mein plug karo. Numerator $2 π ε h$ Ex 1 wala same prefactor hai. Step 3. $exp$ se log undo karo: $b / a = e^{0.2711} = 1.3114 \Rightarrow b = 2.5 \times 1.3114 = 3.278 μ m$ . Yeh step kyun? $ln$ aur $e^{x}$ inverses hain — $e^{0.2711}$ answer karta hai "is log ka ratio kya hai?" Step 4. Minimum liner thickness $= b - a = 3.278 - 2.5 = 0.778 μ m$ . Yeh step kyun? Oxide woh ring hai core aur outer radius ke beech.

Verify: $b = 3.278$ back plug karo: $ln (3.278/2.5) = ln (1.3112) = 0.2710$ , deta hai $C = 1.0844 \times 1 0^{- 14} /0.2710 = 4.00 \times 1 0^{- 14}$ F $= 40$ fF. ✓ Aur $3.278$ , forecast ke mutabiq $3$ aur $3.5$ ke beech land karta hai. ✓ Kyunki $C$ , $b$ ke saath decrease karta hai, koi bhi $b \geq 3.278 μ m$ condition $C \leq 40$ fF satisfy karta hai — toh yeh truly minimum hai.

Recall Quick self-test (jawab dene ke baad reveal karo)

Jab oxide vanishingly thin ho jaata hai ( $b \to a$ ), TSV capacitance zero hoti hai ya infinity? ::: Infinity — $ln (b / a) \to 0$ denominator mein (Ex 2). Jab wafer zero thickness tak grind ho jaata hai ( $h \to 0$ ), $C$ ka kya hota hai? ::: Yeh zero ho jaata hai, cleanly aur continuously (Ex 3). Full-face TSV I/O, edge I/O ko $L / (4 p)$ factor se kyun beat karta hai? ::: Face count area $L^{2}$ ki tarah badhta hai jabki edge count perimeter $4 L$ ki tarah; unka ratio $L / (4 p)$ hai (Ex 6). $C$ ghataane ke liye oxide thick karte ho — returns diminish kyun hote hain? ::: $C$ , $ln (b / a)$ par depend karta hai, toh gap double karne se log 2× se kam badhta hai (Ex 5).

Connections

Parent: 3D stacking and through-silicon vias (TSV) (index 6.5.3)
Bandwidth payoff: High Bandwidth Memory (HBM)
Wire-delay motivation: Interconnect RC Delay, Moore's Law
The thermal wall: Thermal Management in ICs
Alternatives & context: Interposers and 2.5D Integration, Chiplets and Heterogeneous Integration, Chip Packaging

Worked examples — 3D stacking and through-silicon vias (TSV)