Etch karo ek deep narrow hole (via) using Deep Reactive-Ion Etching (DRIE / Bosch process) — alternating etch + passivation se near-vertical walls milti hain.
Line karo wall ko ek insulating oxide se (silicon semiconducting hai; iske bina via substrate se short ho jaata hai) + ek barrier (jaise TaN, copper ko silicon mein diffuse hone se rokta hai jo transistors ko poison karta).
Fill karo copper se electroplating ke zariye.
Thin karo wafer ko back se (grind down to tens of µm) taaki via ab bottom se bahar nikle → "via reveal."
Bond karo next die se microbumps ya hybrid Cu–Cu bonding se.
TSV ka full form kya hai aur yeh physically kya karta hai?
Through-Silicon Via — ek metal-filled vertical tunnel silicon die se guzarta hua jo isko upar/neeche stacked die se connect karta hai.
TSV mein oxide liner kyun honi chahiye?
Silicon semiconducting hai; insulation ke bina copper substrate se short ho jaata (aur copper diffuse hokar transistors ko poison karta → isliye barrier bhi chahiye).
TSV capacitance formula aur iska coax analogy do.
C=ln(b/a)2πεh; core=copper radius a, oxide to b, grounded silicon bahar — ek coaxial capacitor.
3D integration mein wafer thin kyun karte hain?
Via length h chhoti hoti hai, jo CTSV kam karta hai (faster, lower-energy) aur bonding ke liye via bottom reveal karta hai.
3D stacking 2D se zyada bandwidth kyun deta hai?
2D I/O edge se nikalti hai (∝ L, perimeter); 3D I/O poora face use karta hai (∝ L², area) → bahut zyada parallel links (HBM ki wide bus ka basis).
Wire delay length² kyun scale karta hai?
Wire ka R aur C dono length ke saath scale karte hain, aur delay ∝ RC ∝ length².
3D stacking ka #1 limiter kya hai?
Heat/thermal density — power fixed footprint mein multiply hoti hai lekin buried layers heat dump nahi kar sakti.
2.5D aur 3D integration mein farq?
2.5D: dies ek interposer par side-by-side (TSVs interposer mein). 3D: dies directly stacked, TSVs active dies se guzarte hain.
Keep-out zone (KOZ) kya hai?
TSV ke around area jahan koi transistors nahi rakhe jaate, kyunki TSV thermo-mechanical stress device performance degrade karta hai.
TSVs drill karne ke liye use hone wala etch process batao.
Deep Reactive-Ion Etching (DRIE / Bosch process) near-vertical high-aspect-ratio holes ke liye.
Recall Feynman: 12-saal ke bachche ko samjhao
Socho ek sheher jahan har ghar ek flat street par hai. Dost ko letter bhejna ho toh poore sheher ke paar jaata hai — slow aur thaka dene wala. Ab socho ghar ek tall apartment block mein hain: tera dost seedha tere upar waale floor par rehta hai, toh bas ceiling mein ek tiny pipe banaao aur letter giraao — instant! TSV wahi pipe hai floor/ceiling se, aur 3D stacking chips ko apartment floors ki tarah stack karna hai. Sirf problem yeh hai: bahut saare hot floors ek saath pack karo toh beech waale apartments bahut garam ho jaate hain, toh forever stack nahi kar sakte.
