Full custom vs standard cell design — Hardware notes

WHY does this distinction even exist?

The whole spectrum exists because of three competing pressures:

Pressure	Pulls you toward
Performance / area / power must be extreme	Full custom
Time-to-market must be short	Standard cell
Design cost (engineer-hours) must be low	Standard cell

WHAT each methodology actually is

The key enabling constraint of standard cells:

Figure — Full custom vs standard cell design

HOW they compare (the exam table)

Attribute	Full Custom	Standard Cell
Who draws transistors	Human	Library (pre-made)
Placement & routing	Manual	Automated (P&R tool)
Design time / cost	Very high	Low–moderate
Performance	Highest	Good
Area (density)	Highest	Moderate (wasted rows/whitespace)
Flexibility	Total	Limited to library
Error-prone?	Yes (manual)	Low (verified cells)
Typical use	CPU datapaths, analog, RAM, I/O	Random logic, ASICs, control
NRE cost	Very high	Lower

Deriving the trade-off quantitatively (from first principles)

We don't just memorize "full custom is denser." Let's build a simple model so we can reason.

Forecast-then-Verify

Recall Predict BEFORE reading on: which methodology gives higher

density, and which gives faster time-to-market? Which does a modern SoC actually use? Density winner: Full custom (hand-optimized packing). Time-to-market winner: Standard cell (automated P&R, verified library). Real SoC: a hybrid — custom for datapath/memory/analog, standard cell for control/random logic.

Common mistakes (Steel-manned)

Flashcards

What defines full custom design?

Manual layout of every individual transistor and interconnect, optimized by hand for a specific function.

What defines standard cell design?

A semi-custom style using a library of pre-characterized, fixed-height logic cells assembled automatically by place-and-route tools.

Why must standard cells share a fixed height?

So cells align into rows with abutting power/ground rails, enabling automated placement & routing of millions of gates.

Which methodology gives the highest density and performance?

Full custom.

Which methodology gives the shortest time-to-market and lowest design cost?

Standard cell.

Give the break-even transistor count between the two on design time.

N^* = L/(t_c - t_s)

, where

L

=library cost,

t_c

t_s

=per-transistor custom/stdcell effort.

Why is standard-cell area larger for the same logic?

Lower density from routing channels/whitespace and generically-sized cells; area

\propto 1/\text{density}

Where in a real SoC is full custom typically used?

Datapaths/ALUs, SRAM/memory bit-cells, analog blocks, PLLs, high-speed I/O.

Where is standard cell typically used?

Random/control logic and general ASIC glue logic.

Why is full custom worth it for an SRAM 6T cell despite the effort?

The one-time optimization is amortized over millions of replicated copies, multiplying every area/power saving.

How does gate array differ from standard cell?

Gate array pre-fabricates transistors and only customizes wiring/metal layers; standard cell customizes all layers.

Are standard cells "not real hardware layout"?

No — they are real transistor layouts, just drawn once by the library and reused.

Recall Feynman: explain to a 12-year-old

Imagine building with LEGO. Full custom is like sculpting each brick yourself from clay — you can make the perfect shape, but it takes forever. Standard cell is like using a box of ready-made LEGO bricks that all have the same height so they snap together neatly and fast. Ready bricks are quicker and rarely broken, but they don't fit quite as perfectly as a hand-sculpted one. Smart builders sculpt just a few special pieces by hand (the parts that really need to be perfect) and use ready bricks for everything else.

Connections

Semi-custom design — standard cell + gate array both live here
Gate array design — customizes only metal layers
Place and route (P&R) — the tool flow standard cells depend on
Standard cell library characterization — how cells get timing/power models
ASIC design flow — RTL → synthesis → P&R uses standard cells
SRAM design — classic full-custom bit-cell
Datapath design — bit-sliced custom layout
Design productivity gap — the "why automate" driver
Non-recurring engineering (NRE) cost — the economic lever

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, chip banane ka matlab hai silicon par transistors aur wires ke rectangles draw karna. Ab do tareeke hain. Full custom matlab har ek transistor tum apne haath se, perfectly, draw karte ho — jaise bespoke suit silwana. Isme performance aur density sabse best hoti hai, par time aur mehnat bahut zyada. Standard cell matlab ek ready-made library (INV, NAND, DFF wagairah) use karke, tool khud placement aur routing kar deta hai — jaise ready-made kapde le lena, fast aur reliable, par thoda fit compromise.

Standard cell ka jaadu ek simple rule se aata hai: saare cells ki height fixed hoti hai. Isliye woh neat rows mein line up ho jaate hain, aur $V_{DD}$ / $GND$ rails automatically abut karke connect ho jaate hain. Yehi cheez tool ko millions of gates place karne deti hai bina human ke. Full custom is rule ko todke extra density nikaalta hai, par phir sab manual ho jaata hai.

Maths se socho: custom ka effort $N t_c$ (har transistor pe steep cost), standard cell ka $L + N t_s$ (ek baar library cost $L$ , phir per gate almost free). Break-even $N^* = L/(t_c - t_s)$ . Jitna bada block, utna standard cell jeetega. Isiliye control logic → standard cell.

Par ek twist: SRAM bit-cell jaisi chhoti cheez jo millions of baar copy hoti hai, usme full custom karo — kyunki ek baar ki mehnat har copy pe multiply ho jaati hai. Isliye real chip hybrid hoti hai: datapath/memory/analog full custom, baaki standard cell. Exam mein table yaad rakho: custom = best performance/area par slow/costly; standard cell = fast/cheap par thoda bada/dheela.

Test yourself — VLSI Design

Connections