FPGA vs ASIC design flow
WHY do two flows exist at all?
WHAT we want: turn a behavioral description of a digital system into a working physical chip.
WHY the split: there is a deep engineering trade-off between flexibility and efficiency.
- If you build the exact transistors for your design (ASIC), you get the smallest, fastest, lowest-power chip — but you pay a huge one-time cost (masks, fabrication) and cannot change it once made.
- If you use a generic reprogrammable chip (FPGA), you can change the design in seconds and pay almost nothing up front — but the generic-ness costs you area, speed, and power.
The shared front end
Common early steps (identical for both):
- Specification — what the chip must do.
- RTL design — write Verilog/VHDL.
- Functional / RTL simulation — verify behavior before any hardware detail.
- Logic synthesis — translate RTL into a netlist of gates.
The divergence begins at synthesis, because what you synthesize to differs.
Where the flows split
FPGA-specific back end
| Step | WHAT it does | WHY needed |
|---|---|---|
| Technology mapping | Pack logic into LUTs | LUTs are the atomic compute unit |
| Place | Assign each LUT/FF to a physical tile | Chip has fixed tile grid |
| Route | Connect tiles via programmable switch fabric | Wires are pre-built but must be selected |
| Bitstream generation | Produce config bits | Bits set every LUT truth-table & switch |
| Configure/Program | Load bitstream into SRAM cells | Chip "becomes" your circuit; erased on power-off |
ASIC-specific back end
| Step | WHAT it does | WHY needed |
|---|---|---|
| Floorplanning | Allocate chip regions | Physical area is being created |
| Place & Route | Position & wire standard cells | Custom metal layers |
| Clock Tree Synthesis (CTS) | Build balanced clock network | Real wire delay must be equalized |
| Static Timing Analysis (STA) | Verify timing with real parasitics | No re-spin allowed |
| DRC / LVS | Design-Rule & Layout-vs-Schematic checks | Fab will reject illegal geometry |
| GDSII → Tape-out → Fab | Send masks to foundry | Physically etch silicon |
Worked examples
Common mistakes (steel-manned)
Flashcards
At which step do the FPGA and ASIC flows first diverge?
What is the atomic compute element mapped to on an FPGA?
What does an ASIC map logic to instead of LUTs?
What is the final output of the FPGA back end?
What is the final output of the ASIC back end?
Write the total cost model.
Derive the break-even volume formula.
Why is a post-fab bug catastrophic for ASIC but cheap for FPGA?
What does CTS (Clock Tree Synthesis) do, and why is it ASIC-specific?
Difference between bitstream and GDSII?
Why are most FPGAs volatile?
Below break-even volume, which technology wins and why?
Recall Feynman: explain to a 12-year-old
Imagine you invented a Lego robot. You have two ways to build a real one. Way 1 (FPGA): buy a magic box already full of tiny switches. You just flip the switches so the box pretends to be your robot. If you made a mistake, flip them again — done in a minute. The box is a bit chunky and slow, and it forgets everything when you unplug it. Way 2 (ASIC): send your blueprint to a factory that melts sand and builds the exact robot chip. It's tiny, super fast, sips power — but costs a fortune to set up and if the blueprint had a typo, you throw it away and pay again. Both start from the same drawing of the robot. They only differ in how the drawing becomes a real thing.
Connections
- RTL Design & Verilog — the shared source both flows synthesize.
- Logic Synthesis — the gate-level netlist that feeds both back ends.
- Lookup Tables (LUTs) & FPGA Architecture — FPGA mapping target.
- Standard Cell Libraries — ASIC mapping target.
- Static Timing Analysis — critical in the ASIC back end.
- Place and Route — shared concept, different physical meaning.
- Non-Recurring Engineering (NRE) Cost — drives the volume decision.
- GDSII & Tape-out — the ASIC hand-off to the fab.
Concept Map
Hinglish (regional understanding)
Intuition Hinglish mein samjho
Dekho, FPGA aur ASIC dono ka shuruaat same hota hai: tum spec likhte ho, phir Verilog/VHDL me RTL banate ho, simulate karke check karte ho, aur synthesis se gate-level netlist nikalte ho. Yahan tak dono bilkul ek jaise chalte hain. Difference tab shuru hota hai jab logic ko real hardware me daalna hota hai — isko technology mapping kehte hain.
FPGA ek pehle se bana hua chip hai jisme laakhon LUTs (Look-Up Tables) aur programmable wires already maujood hain. Tum sirf ek bitstream banate ho jo in switches ko set kar deta hai — chip tumhare circuit jaisa "behave" karne lagta hai. Galti ho gayi? Bas dubara compile karke bitstream reload — 5 minute ka kaam. Lekin ye generic hone ki wajah se thoda slow, zyada power-hungry, aur power off hone par bhool jaata hai (SRAM-based, volatile).
ASIC me tum custom transistors banwate ho. Output hota hai GDSII masks jo factory (fab) me bhejte ho, aur wahan silicon me tumhara exact circuit etch hota hai. Result: sabse chhota, fastest, lowest-power chip — par setup ka NRE cost lakhon-crores me, aur agar bug reh gaya to poora mask dubara — mahine aur paise dono barbaad.
Decision ka asli funda volume hai. Cost formula: . FPGA ka NRE ~0 par per-unit mehnga; ASIC ka NRE bada par per-unit sasta. Break-even . Isse kam units chahiye to FPGA, zyada chahiye to ASIC. Yaad rakho: "same front, different back."