FPGA vs ASIC design flow: Visual walkthrough — Hardware deep dive

We only need one idea from the parent note: both technologies ship the same logic, but they pay for it differently. Everything below turns that sentence into geometry.

Step 1 — What is a "cost", and what is $N$ ?

WHAT. Before any formula, fix the two quantities we will draw.

$N$ = the number of chips you plan to ship. A plain count: 1, 100, a million. This will be our horizontal axis.
$C$ = the total dollars you spend to ship those $N$ chips. This will be our vertical axis.

WHY. Every decision in this chapter is "how much money for how many chips?". If we can plot money vs count, the answer becomes a place on a graph — not an argument.

PICTURE. Just the empty stage: an axis of chips going right, an axis of dollars going up. Nothing drawn yet — we earn every line.

Step 2 — The two kinds of money

WHAT. Split every dollar you will ever spend into exactly two buckets:

One-time money — paid once, no matter how many chips you make. Design tools, verification, and (for ASIC) the photomask set the foundry needs. We call this $C_{NRE}$ (Non-Recurring Engineering — "non-recurring" literally means does not repeat). See Non-Recurring Engineering (NRE) Cost.
Per-chip money — paid again for every single chip. The silicon, the packaging, the testing of that one unit. We call this $c_{unit}$ .

WHY. Why only two buckets and not three? Because there is no third kind of spending: a dollar is either paid once (fixed) or paid per-piece (variable). Any real invoice sorts into one of these. That completeness is what makes the model exact, not approximate.

PICTURE. Two jars on the chalkboard: a fat fixed jar you fill once, and a small jar you refill for every chip that rolls off the line.

Step 3 — Assembling the total-cost line

WHAT. Total money = fill the fixed jar once, then pour the per-chip jar $N$ times: $C_{total} (N) = paid once C_{NRE} + how many chips N \cdot cost of each c_{unit}$

WHY multiplication and addition, nothing fancier? Because "the same cost $c_{unit}$ , repeated $N$ times" is the definition of $N \cdot c_{unit}$ — multiplication is repeated addition. Then we add the one-time jar on top. No exponents, no curves: each extra chip adds the same amount, so the graph is a straight line.

PICTURE. A straight line. Where it touches the vertical axis (at $N = 0$ , zero chips) it already sits at height $C_{NRE}$ — that is the fixed jar, paid before a single chip exists. Its steepness (how fast it climbs as you move right) is exactly $c_{unit}$ : one step right = climb by $c_{unit}$ .

Step 4 — Drawing the FPGA line and the ASIC line together

WHAT. Now draw two of these lines on the same axes, one per technology.

FPGA: starts almost at the floor ( $C_{NRE}^{F} \approx 0$ — you buy a chip that already exists, no masks), but climbs steeply (large $c_{u}^{F}$ — each chip is a whole generic part).
ASIC: starts high (huge $C_{NRE}^{A}$ — you pay for the mask set and tape-out before chip #1), but climbs shallowly (tiny $c_{u}^{A}$ — bare custom silicon is cheap per piece).

The superscripts $F$ and $A$ just tag which technology a number belongs to. $C_{NRE}^{A}$ = "the once-jar, for ASIC."

WHY two lines? Because the whole decision is a comparison. One line alone tells you a cost; two lines let you ask "which is lower — and where?"

PICTURE. Two chalk lines: the FPGA line low-start / steep, the ASIC line high-start / shallow. A steep line and a shallow line that start at different heights must cross exactly once (or never) — that crossing is the whole story.

Step 5 — The crossing point: where the two lines are equal

WHAT. The crossing is the $N$ where both technologies cost the same. Set the two heights equal: $C_{NRE}^{F} + N c_{u}^{F} = C_{NRE}^{A} + N c_{u}^{A}$

WHY set them equal? "Equal cost" is literally the point where switching your choice makes no difference — the break-even. To the left of it one technology is cheaper; to the right, the other. Finding that one $N$ splits the whole number line into "FPGA-land" and "ASIC-land."

PICTURE. Zoom into the intersection. Left of it the FPGA line is lower (cheaper); right of it the ASIC line dips below. The vertical grid-line dropped from the crossing marks the special volume we will call $N^{*}$ .

Step 6 — Solving for $N^{*}$ by pure rearranging

WHAT. Untangle the equation from Step 5 to get $N$ alone. Move every $N$ -term to one side, every fixed term to the other: $N c_{u}^{F} - N c_{u}^{A} = C_{NRE}^{A} - C_{NRE}^{F}$ Factor $N$ out of the left side (it appears in both terms): $N (c_{u}^{F} - c_{u}^{A}) = C_{NRE}^{A} - C_{NRE}^{F}$ Divide both sides by the bracket to isolate $N$ : $N^{*} = \frac{C _{NRE}^{A} - C _{NRE}^{F} extra fixed cost of ASIC}{saving per chip c _{u}^{F} - c _{u}^{A}}$

WHY divide fixed-difference by per-chip-difference? Read the fraction as a sentence: "how much extra you paid up front" ÷ "how much you claw back on each chip" = "how many chips until you've clawed it all back." That is exactly a break-even count. Dividing a total by a per-item amount always answers "how many items?".

PICTURE. The numerator drawn as the vertical gap between where the two lines start (the extra ASIC fixed cost). The denominator drawn as the gap in steepness (how much faster the FPGA line climbs). Big head-start gap ⇒ need more chips; big steepness gap ⇒ catch up sooner.

Step 7 — Which side wins? Reading the two regions

WHAT. Split the axis at $N^{*}$ :

$N < N^{*}$ → you haven't shipped enough chips to repay ASIC's fixed head-start → FPGA is cheaper.
$N > N^{*}$ → the per-chip savings have overtaken the fixed cost → ASIC is cheaper.
$N = N^{*}$ → a dead tie; pick on other grounds (time-to-market, ability to reprogram).

WHY. Because to the left the ASIC line still sits above the FPGA line, and to the right it has dropped below. The crossing is the only place the answer flips.

PICTURE. The plane shaded into two coloured zones with $N^{*}$ as the fence: a blue FPGA-wins region on the left, a pink ASIC-wins region on the right.

Step 8 — The degenerate & edge cases (never let the reader fall through)

WHAT & WHY. A formula you trust must survive its extremes. Four cases:

$N = 0$ (ship nothing). $C^{F} = C_{NRE}^{F} \approx 0$ , $C^A=C^A_{\text{NRE}}=\$ 1\text{M}$. FPGA wins trivially — you'd never pay a million dollars in masks to build zero chips.
$c_{u}^{F} = c_{u}^{A}$ (equal per-chip cost). The denominator of $N^{*}$ becomes $0$ → division by zero → no crossing. The two lines are parallel; the lower-starting FPGA is always cheaper. This is why ASIC needs a genuine per-chip advantage to ever make sense.
$C_{NRE}^{A} = C_{NRE}^{F}$ (equal fixed cost). Numerator $= 0$ → $N^{*} = 0$ . The lines meet at the very start, and ASIC (shallower slope) wins for all $N > 0$ .
A bug found after tape-out. For ASIC this silently resets $C_{NRE}^{A}$ upward — a whole new mask set — shoving the ASIC line up and pushing $N^{*}$ to the right. For FPGA a bug just means reloading a bitstream: $C_{NRE}^{F}$ barely moves. Risk is a hidden term in the fixed jar.

PICTURE. Three mini-panels: parallel lines (case 2, never cross), lines meeting at the origin (case 3), and the ASIC line jumping upward after a re-spin (case 4).

The one-picture summary

Everything on this page is two straight lines and where they meet.

Recall Feynman retelling — say it like you'd explain it to a friend

Imagine two ways to pay for chips. The FPGA way: you walk in owing almost nothing, but every chip is pricey — so your bill climbs fast. The ASIC way: you hand over a giant cheque up front (for the masks), but after that each chip is dirt cheap — so your bill climbs slowly.

Plot "total money" going up and "number of chips" going right. FPGA is a low-start, steep line. ASIC is a high-start, shallow line. A steep line starting low and a shallow line starting high always cross once. Before the crossing, the FPGA line is underneath — FPGA is cheaper. After it, the ASIC line dips under — ASIC is cheaper.

To find the crossing, ask: "How much extra did I pay up front for ASIC, and how much do I save per chip?" Divide the first by the second — that many chips is exactly when the per-chip savings have paid back the up-front cheque. That number is $N^{*}$ . Fewer chips than $N^{*}$ : go FPGA. More: go ASIC. And if ASIC saves nothing per chip, the lines never cross and FPGA always wins — which is the whole reason ASIC only makes sense at high volume.

Recall

The break-even $N^{*}$ divides the plane into two regions — what are they? ::: Left of $N^{*}$ (fewer chips) FPGA is cheaper; right of $N^{*}$ (more chips) ASIC is cheaper. Why is each total-cost curve a straight line and not a curve? ::: Every extra chip adds the same fixed amount $c_{u ni t}$ , and repeated equal additions form a line with slope $c_{u ni t}$ and intercept $C_{N R E}$ . What does the numerator of $N^{*}$ mean physically? ::: The extra one-time (NRE) cost you take on by choosing ASIC over FPGA. What does the denominator of $N^{*}$ mean physically? ::: The money ASIC saves you on each chip ( $c_{u}^{F} - c_{u}^{A}$ ). If $c_{u}^{F} = c_{u}^{A}$ , what happens to $N^{*}$ and why? ::: The denominator is zero, so there is no crossing — the lines are parallel and FPGA (lower start) always wins.