Intuition The one core ideaA digital chip design is just a description (what the circuit should do ) that gets slowly turned into physical stuff (transistors and wires that actually do it). FPGA and ASIC are two different endings to the same story: one configures a chip that already exists , the other manufactures a brand-new chip — and every symbol on the parent page exists only to describe, or to price, that one journey.
Before you can compare two design flows, you must be able to read the words inside those flows. This page builds every one of them from nothing, in an order where each idea rests on the one before it. Nothing here assumes you have seen a chip, a gate, or a formula.
Everything on the parent page lives somewhere on a single road that runs from an idea in your head to a physical chip in your hand . Look at the road first; every term below is a signpost on it.
Intuition Read the road left to rightOn the left you have pure meaning — "I want a circuit that adds two numbers." On the right you have matter — actual silicon. Every design step moves you rightward, trading abstraction for physical detail. The FPGA and ASIC paths only differ on the right half of this road.
Definition Digital signalA wire that is only ever allowed to be in one of two states : a low voltage (call it 0 high voltage (call it 1
Picture: a light switch. Not a dimmer — a switch. Off is 0 1
Why the topic needs it: the whole chip is a giant machine that shuffles 0 1
A tiny device that takes one or more digital inputs and produces a digital output by a fixed rule. The three you must know:
AND — output is 1 1 OR — output is 1 1 NOT — output is the opposite of its single input.
Why the topic needs it: when the parent says "synthesis translates RTL into a netlist of gates ," these are the gates. A netlist is nothing more than a huge pile of AND/OR/NOT wired together.
Intuition Why gates and not equations?A gate is chosen over ordinary algebra because a gate is something you can physically build from a few transistors . Every rule a computer follows must eventually become a switch that is open or closed — and a gate is the smallest such switch-rule.
A special wire that ticks: 0 , 1 , 0 , 1 , … 0 1 clock edge — the heartbeat that tells the circuit "now is the moment to remember something."
Picture: a metronome. Every tick, the whole chip takes one synchronized step.
Definition Register (flip-flop)A one-bit memory box. On each clock edge it captures whatever value is on its input and holds it until the next edge. Written with the symbol you will see as FF (flip-flop).
Picture: a bucket under a tap. The tap drips only on the tick; between ticks the bucket just holds its water.
Why the topic needs it: this is the "Register " in Register-Transfer Level . Registers are the resting points; combinational gates are the roads between them.
Definition Combinational logicLogic made only of gates, with no memory . Its output depends only on its inputs right now. Between two clock edges, this is what computes "the next value."
Definition RTL (Register-Transfer Level)A way of describing a circuit as: registers , plus the combinational logic that computes each register's next value between clock edges. You write it in a language called Verilog or VHDL .
Intuition Why "register-transfer"?Look at the figure: a value sits in a register, is transferred through a cloud of combinational gates, and lands in the next register on the following tick. The whole chip is registers passing data to registers — hence the name. See RTL Design & Verilog for how the text is actually written.
Why the topic needs it: RTL is the one thing FPGA and ASIC share . Both flows begin from the exact same RTL — that shared start is the entire reason the parent page can compare them fairly.
A flat list of every gate in the design and every wire connecting them. No behaviour, no "if/else" — just components and connections, like a parts list plus a wiring diagram.
Definition Logic synthesisThe automatic step that reads your RTL (behaviour) and produces a netlist (gates + wires) that behaves the same way. It "compiles" meaning into hardware structure. See Logic Synthesis .
Why the topic needs it: the parent says the flows "diverge at synthesis, because what you synthesize to differs ." You cannot understand the divergence until you know that synthesis outputs a netlist — and that the netlist can be built from two different kinds of parts , covered next.
Here is the fork in the road. A netlist of AND/OR/NOT gates must be built from real primitives . There are exactly two families.
Definition LUT (Look-Up Table)A tiny pre-built memory that acts like any small logic gate you want. You fill its truth table (its list of outputs) with bits, and it copies whatever gate those bits describe.
Picture: a cheat-sheet. Give it the inputs, it looks up the answer you pre-wrote. Change the written answers → it becomes a different gate, no rewiring. See Lookup Tables (LUTs) & FPGA Architecture .
A pre-designed physical gate (an actual AND, an actual flip-flop) from a catalogue called a standard-cell library . To use one, the factory literally prints its transistors onto silicon.
Intuition The whole FPGA-vs-ASIC split in one contrast
LUT — the hardware already exists ; you only choose the bits inside it. This is the FPGA world.Standard cell — the hardware does not exist yet ; you manufacture it. This is the ASIC world.
Everything the parent page calls "technology mapping" is just: which family of parts do I build my netlist from?
These terms appear in the parent's two back-end tables. Each is one physical action.
Decide where each part physically sits on the chip. (FPGA: on a fixed grid of tiles. ASIC: anywhere in a region you are creating.)
Decide which wires connect the placed parts. FPGA picks from pre-built switch wires; ASIC draws brand-new metal. See Place and Route .
Definition Static Timing Analysis (STA)A check that every signal arrives before the next clock tick . It does not run the chip; it computes worst-case delays from the wiring. See Static Timing Analysis . Needed hardest on ASIC because "no re-spin allowed."
The FPGA's final output: a long list of configuration bits that fill every LUT's truth table and set every routing switch. Loading it makes a generic chip "become" your circuit.
Definition GDSII / Tape-outThe ASIC's final output: a file describing the exact shapes (geometry) the factory will etch into silicon to build your transistors. Sending it out is called tape-out . See GDSII & Tape-out .
Common mistake Bitstream and GDSII feel like "the same final file."Why it feels right: both are the last thing you produce.
Fix: a bitstream configures hardware that already exists ; a GDSII manufactures hardware that does not exist yet . One dials a lock, the other casts a key.
The parent's decision is priced with a formula. Every symbol in it is defined here.
Definition The cost alphabet
N number of chips you plan to ship. A plain counting number.c unit one chip (the "per-piece" price).C NRE N on-R ecurring E ngineering cost: money you pay exactly once (masks, tools, verification), no matter how many chips you make. See Non-Recurring Engineering (NRE) Cost .
Intuition Why this is a straight linePlot cost against N C NRE c unit
Synthesis makes a netlist
Cover the right side and test yourself. If you can answer all, you are ready for the flow comparison and the cost maths.
What are the only two values a digital signal may take? Low = 0 1
What does an AND gate output? 1 1
What does a register do on a clock edge? Captures its input value and holds it until the next edge.
In "Register-Transfer Level", what is being transferred? A value moving from one register, through combinational logic, into the next register.
What is a netlist? A flat list of every gate and every connecting wire — structure, not behaviour.
What does logic synthesis produce from RTL? A netlist of gates that behaves the same as the RTL.
What is a LUT and why can it act as any small gate? A tiny memory whose truth-table bits you fill in; changing the bits changes which gate it imitates.
How does a standard cell differ from a LUT? A standard cell is a physical gate that must be manufactured; a LUT already exists and is only configured.
What does a bitstream do? Fills every LUT's truth table and sets every routing switch to configure an existing FPGA.
What does GDSII describe? The exact geometry a fab etches into silicon to manufacture an ASIC.
What does C NRE Non-Recurring Engineering cost — a one-time fixed charge, paid once regardless of how many chips you make.
Write the total cost model. C total ( N ) = C NRE + N ⋅ c unit
Return to the parent: FPGA vs ASIC design flow .
