FPGA vs ASIC design flow: Worked examples — Hardware deep dive

The scenario matrix

Think of every question as a point on a straight-line graph: cost on the vertical axis, quantity $N$ on the horizontal. FPGA is a steep line starting at ~zero; ASIC is a shallow line starting high up. They cross once, at $N^{*}$ .

How to read this figure: the horizontal axis is $N$ (thousands of chips), the vertical axis is total cost in millions of dollars. The cyan line is the FPGA — it starts at the origin (no mask cost) and climbs steeply because each chip is expensive. The amber line is the ASIC — it starts high up at $1 M (the mask NRE) but climbs gently because each chip is cheap. They meet at the white dot labelled $N^{*} = 28, 571$ . Notice the shaded verdict text: left of the dashed line the cyan line is lower (FPGA cheaper); right of it the amber line is lower (ASIC cheaper). Every example below is just "which side of that white dot am I on?"

Every case class below is just where you land relative to that crossing point, or what happens when an input is extreme/zero.

Cell	Case class	What makes it special	Covered by
A	$N < N^{*}$ (FPGA side)	not enough volume to repay masks	Ex 1
B	$N > N^{*}$ (ASIC side)	volume repays masks & then some	Ex 2
C	$N = N^{*}$ exactly	tie — the degenerate boundary	Ex 3
D	$c_{u}^{F} = c_{u}^{A}$ (zero denominator)	lines parallel → no crossing	Ex 4
E	Non-zero FPGA NRE (dev-board/tools)	numerator uses difference of NREs	Ex 5
F	Solve for a target price not a choice	invert the model for $c_{unit}$	Ex 6
G	Real-world word problem	translate English → symbols	Ex 7
H	Time / re-spin cost (not just $)	bug-after-tape-out limiting case	Ex 8
I	Negative denominator ( $c_{u}^{F} < c_{u}^{A}$ )	$N^{*} < 0$ → no valid crossing	Ex 9
J	Exam twist: volume ramp over time	piecewise decision, when to switch	Ex 10
K	$C_{N R E}^{A} = C_{N R E}^{F}$ (zero numerator)	$N^{*} = 0$ → lines cross at the origin	Ex 11

Example 1 — Cell A: below break-even

Worked example 8,000 units of a niche instrument

FPGA: $C^{F}_{NRE}=\$ 0 $,$ c^{F}{u}=$50 $. A S I C :$ C^{A}{NRE}=$900{,}000 $,$ c^{A}_{u}=$6$. Forecast: low volume, huge mask cost — guess before reading: FPGA or ASIC?

Step 1 — find the crossing $N^{*}$ . $N^{*} = \frac{900 , 000 - 0}{50 - 6} = \frac{900 , 000}{44} \approx 20, 455$ Why this step? The whole decision is "which side of the crossing are we on?" — so we must locate the crossing first.

Step 2 — compare our volume to it. $8, 000 < 20, 455$ → we are on the FPGA side → choose FPGA. Why this step? Left of the crossing the ASIC line is still above the FPGA line (look at the graph); FPGA is literally cheaper here.

Verify: plug both into $C_{total}$ . FPGA $=0+8{,}000\times50=\$ 400{,}000 $. A S I C$ =900{,}000+8{,}000\times6=$948{,}000 $.$ 400{,}000 < 948{,}000 $✓ — FPGA wins by \$ 548,000, matching the "left of crossing" verdict.

Example 2 — Cell B: above break-even

Example 3 — Cell C: exactly at the boundary (degenerate tie)

Worked example What volume makes them cost

the same, and prove it's a tie Same numbers as Ex 1. We already have $N^{*} = 900, 000/44$ . Forecast: at $N = N^{*}$ what should the two total costs be? Equal — but let's see it.

Step 1 — keep $N^{*}$ exact. $N^{*} = \frac{900 , 000}{44} = \frac{225 , 000}{11}$ (don't round yet). Why this step? Rounding first would make the "tie" look like a mismatch of a few dollars; exact fractions expose the true equality.

Step 2 — evaluate both lines at $N^{*}$ . FPGA $= 50 \cdot \frac{225 , 000}{11} = \frac{11 , 250 , 000}{11}$ . ASIC $= 900, 000 + 6 \cdot \frac{225 , 000}{11} = 900, 000 + \frac{1 , 350 , 000}{11}$ . Why this step? The definition of $N^{*}$ is exactly where these two are equal — evaluating both is the honest check.

Verify: ASIC $= \frac{9 , 900 , 000 + 1 , 350 , 000}{11} = \frac{11 , 250 , 000}{11} =$ FPGA ✓. Perfect tie — at the crossing the choice is a coin-flip on cost alone (decide on flexibility instead).

Example 4 — Cell D: parallel lines (denominator = 0)

Worked example The dangerous "divide by zero"

Suppose a vendor quotes $c^{F}_{u}=\$ 6 $an d$ c^{A}_{u}=$6 $(e q u a l p er - u ni t), F P G A N R E$ =$0 $, A S I C N R E$ =$900{,}000 $. * * F or ec a s t : * * w ha t i s$ N^{*}$? Try the formula — what breaks?

Step 1 — try the formula. $N^{*} = \frac{900 , 000 - 0}{6 - 6} = \frac{900 , 000}{0} — undefined!$ Why this step? The denominator $c_{u}^{F} - c_{u}^{A}$ is the per-unit saving. If per-unit costs are equal, ASIC saves nothing per chip, so volume can never repay the mask cost. The lines are parallel — they never cross.

Step 2 — decide without a crossing. Since $c_{u}^{F} = c_{u}^{A}$ , compare only the constant terms: FPGA constant $= 0 <$ ASIC constant $= 900, 000$ . So for every $N \geq 0$ , FPGA is cheaper (or equal). Always choose FPGA. Why this step? When slopes match, whichever line starts lower stays lower forever — geometry, not algebra.

Verify: at $N = 1, 000, 000$ : FPGA $= 6, 000, 000$ ; ASIC $= 900, 000 + 6, 000, 000 = 6, 900, 000$ . FPGA still cheaper ✓ even at huge volume — confirming "no crossing."

Example 5 — Cell E: non-zero FPGA NRE

Worked example FPGA also has some fixed cost (dev tools + board bring-up)

FPGA: $C^{F}_{NRE}=\$ 120{,}000 $,$ c^{F}{u}=$45 $. A S I C :$ C^{A}{NRE}=$1{,}500{,}000 $,$ c^{A}_{u}=$5 $. V o l u m e$ =30{,}000$. Forecast: the FPGA no longer starts at zero — does the crossing move left or right?

Step 1 — use the difference of NREs in the numerator. $N^{*} = \frac{1 , 500 , 000 - 120 , 000}{45 - 5} = \frac{1 , 380 , 000}{40} = 34, 500$ Why this step? The numerator is the extra fixed cost of going ASIC, i.e. how much more mask money you must repay — that's the difference, not ASIC's NRE alone. This is the classic trap of ignoring FPGA's own fixed cost.

Step 2 — compare. $30, 000 < 34, 500$ → FPGA. Why this step? Below the (shifted) crossing, FPGA still wins.

Verify: FPGA $=120{,}000+30{,}000\times45=\$ 1{,}470{,}000 $. A S I C$ =1{,}500{,}000+30{,}000\times5=$1{,}650{,}000 $. FPGA cheaper by \$ 180,000 ✓ — matches "below $N^{*}$ ."

Example 6 — Cell F: invert the model (solve for a price)

Worked example "What unit price would make ASIC break even at exactly 50,000 units?"

Fixed: $C_{N R E}^{F} = 0$ , $c^{F}_{u}=\$ 40 $,$ C^{A}{NRE}=$1{,}200{,}000 $. F in d t h e A S I C u ni t cos t$ c^{A}{u} $t ha t g i v es$ N^{*}=50{,}000$. Forecast: we're running the machine backwards — expect algebra, not a plug-in.

Step 1 — write the break-even condition and solve for the unknown. Set the two total costs equal at $N = 50, 000$ : $0 + 50, 000 \cdot 40 = 1, 200, 000 + 50, 000 \cdot c_{u}^{A}$ Why this step? "Break even at 50,000" means the two totals are equal there — that's the equation to invert.

Step 2 — isolate $c_{u}^{A}$ . $2, 000, 000 - 1, 200, 000 = 50, 000 c_{u}^{A} \Rightarrow c_{u}^{A} = \frac{800 , 000}{50 , 000} = $16$ Why this step? Subtract the fixed cost, divide by the volume — the same "fixed ÷ per-unit" structure, just solved for a different letter.

Verify: with $c_{u}^{A} = 16$ : $N^{*} = \frac{1 , 200 , 000}{40 - 16} = \frac{1 , 200 , 000}{24} = 50, 000$ ✓ exactly the target.

Example 7 — Cell G: real-world word problem

Worked example Startup decision under a deadline

"We ship 12,000 smart-camera boards. An FPGA ($70 each, no mask cost) works today. An ASIC would cost $2.0 M in NRE but only $4/chip and take 9 months. We ship in 3 months. Which?" Forecast: translate the English into symbols first — then guess.

Step 1 — extract symbols. $C_{N R E}^{F} = 0, c_{u}^{F} = 70, C_{N R E}^{A} = 2, 000, 000, c_{u}^{A} = 4, N = 12, 000$ . Why this step? Word problems fail when you compute before naming; pin every number to a symbol.

Step 2 — break-even. $N^{*} = \frac{2 , 000 , 000}{70 - 4} = \frac{2 , 000 , 000}{66} \approx 30, 303$ . Why this step? Locate the crossing to see which side 12,000 falls on.

Step 3 — compare and read the non-cost constraint. $12, 000 < 30, 303$ → FPGA cheaper. Also the ASIC needs 9 months but we ship in 3 → ASIC is impossible on schedule. Choose FPGA (both cost and time agree). Why this step? Real decisions add constraints beyond dollars; here time-to-market seals it.

Verify: FPGA $=12{,}000\times70=\$ 840{,}000 $; A S I C$ =2{,}000{,}000+12{,}000\times4=$2{,}048{,}000 $. FPGA cheaper by \$ 1,208,000 ✓, and delivers on time.

Example 8 — Cell H: the re-spin limiting case (a bug appears)

Worked example Cost of a bug found after commit

A logic bug is found after the design is locked. FPGA fix = recompile bitstream ($0 mask, hours). ASIC fix = one mask re-spin at $1.5 M + 4 months, on a project already at 12,000 units of ASIC ( $c_{u}^{A} = 4$ , original NRE $2.0 M). Forecast: a bug turns ASIC NRE into a moving number — guess what happens to $N^{*}$ .

Step 1 — model the re-spin as extra NRE. New ASIC NRE $=2{,}000{,}000+1{,}500{,}000=\$ 3{,}500{,}000 $. * W h y t hi ss t e p ? * A r e - s p ini s a f r es h o n e - t im e ma s k c ha r g e \to i t a dd s t o$ C^{A}{NRE} $, t h e f i x e d t er m, n o t$ c^{A}{u}$.

Step 2 — recompute the crossing (FPGA at $70, NRE 0). $N^{*} = \frac{3 , 500 , 000 - 0}{70 - 4} = \frac{3 , 500 , 000}{66} \approx 53, 030$ Why this step? The bug pushed the crossing far to the right — ASIC now needs far more volume to justify itself.

Verify: the crossing moved from $\approx 30, 303$ (Ex 7 numbers) to $\approx 53, 030$ , i.e. rightward by $\approx 22, 727$ units ✓. This is the mathematical face of "an ASIC bug is catastrophic": each re-spin shoves break-even out of reach, whereas the FPGA line never moved at all.

Example 9 — Cell I: negative denominator ( $N^{*} < 0$ )

Worked example A quote where the ASIC costs

more per chip A shady vendor quotes FPGA: $C^{F}_{NRE}=\$ 0 $,$ c^{F}{u}=$8 $; A S I C :$ C^{A}{NRE}=$500{,}000 $,$ c^{A}_{u}=$20 $(y es — t h e A S I C i s * d e a r er p er u ni t *, e . g . t in y w a f er v o l u m e w i t ha cos tl y p r ocess) . * * F or ec a s t : * * t h e A S I C cos t s m or e * b o t h * u p f r o n t * an d * p er c hi p — d oes a cr oss in g e v e n e x i s t ? C o m p u t e$ N^{*}$ and interpret the sign.

Step 1 — plug into the formula and read the sign. $N^{*} = \frac{500 , 000 - 0}{8 - 20} = \frac{500 , 000}{- 12} \approx - 41, 667$ Why this step? The denominator $c_{u}^{F} - c_{u}^{A} = 8 - 20 = - 12$ is negative — the "per-unit saving" of going ASIC is negative (you lose $12 per chip). A negative $N^{*}$ is a warning flag, not a shippable volume (you can't make −41,667 chips).

Step 2 — interpret: no valid crossing. A negative $N^{*}$ means the two lines only "cross" at a negative $N$ , which is off the real chart ( $N \geq 0$ ). For every real volume, ASIC's line sits above FPGA's (it starts higher and rises faster). Always choose FPGA here. Why this step? When both the start point and the slope favour FPGA, ASIC never catches up — the algebra's negative sign is just telling you "the crossing is in the impossible region."

Verify: at $N = 100, 000$ : FPGA $=0+100{,}000\times8=\$ 800{,}000 $; A S I C$ =500{,}000+100{,}000\times20=$2{,}500{,}000 $. ASIC dearer by \$ 1.7 M ✓, and the gap only widens with $N$ — confirming no real-world crossing.

Example 10 — Cell J: exam twist, decision over a volume ramp

Worked example Volume grows year by year — when should you

switch to ASIC? A product ships $N_{1} = 5, 000$ in year 1, then a cumulative $N_{2} = 45, 000$ by year 2. FPGA: $0 NRE, $40/unit. ASIC: $1.0 M NRE, $5/unit ( $N^{*} = 1, 000, 000/35 \approx 28, 571$ from the parent note). Forecast: two checkpoints straddle the crossing — guess which year flips the answer.

Step 1 — confirm the crossing. $N^{*} = \frac{1 , 000 , 000 - 0}{40 - 5} = \frac{1 , 000 , 000}{35} \approx 28, 571$ Why this step? We need the trigger volume before we can say when the ramp passes it.

Step 2 — test the year-1 cumulative volume. $5, 000 < 28, 571$ → FPGA. Why this step? Early cumulative volume is below break-even, so stay flexible & cheap.

Step 3 — test the year-2 cumulative volume. $45, 000 > 28, 571$ → ASIC becomes cheaper for that volume. Why this step? Once cumulative demand passes the crossing, the shallow ASIC line dips below the steep FPGA line.

Step 4 — read the strategy. Prototype/ship on FPGA in year 1, then migrate to ASIC once the volume forecast crosses $\approx 28, 571$ units. The break-even is the switch trigger, not a one-time verdict. Why this step? Real teams don't pick once forever; they pick per-volume-regime — exactly what the line-crossing graph encodes.

Verify (year-2 costs at 45,000): FPGA $=45{,}000\times40=\$ 1{,}800{,}000 $; A S I C$ =1{,}000{,}000+45{,}000\times5=$1{,}225{,}000 $. ASIC cheaper by \$ 575,000 ✓ — the flip is real by year 2, confirming the "switch after the crossing" strategy.

Example 11 — Cell K: identical fixed costs (zero numerator, crossing at the origin)

Worked example Both options carry the

same NRE A subsidised prototyping program charges an identical fixed fee for either path: FPGA $C^{F}_{NRE}=\$ 300{,}000 $,$ c^{F}{u}=$40 $; A S I C$ C^{A}{NRE}=$300{,}000 $,$ c^{A}_{u}=$5 $. V o l u m e$ =10{,}000$. Forecast: the fixed costs cancel — where does the crossing land, and who wins for any positive volume?

Step 1 — plug into the formula and read the zero numerator. $N^{*} = \frac{300 , 000 - 300 , 000}{40 - 5} = \frac{0}{35} = 0$ Why this step? The numerator $C_{N R E}^{A} - C_{N R E}^{F}$ is the extra fixed cost of going ASIC. If the two NREs are equal, that extra is zero — there is no mask premium to repay — so the lines meet at $N = 0$ (the origin), not out at some large volume.

Step 2 — decide for every real volume. Both lines start at the same height ( $\$ 300{,}000 $) b u tt h e A S I C s l o p e ($ $5 $) i s g e n tl er t han t h e F P G A s l o p e ($ $40 $) . F r o m t h eor i g in o n w a r d t h e A S I C l in e i s * a l w a y s * l o w er . S o f or * * e v er y * *$ N>0 $, * * c h oose A S I C * *; a t e x a c tl y$ N=0$ they tie. Why this step? When start points are equal, the shallower slope wins immediately — no volume threshold to clear.

Verify: at $N = 10, 000$ : FPGA $=300{,}000+10{,}000\times40=\$ 700{,}000 $; A S I C$ =300{,}000+10{,}000\times5=$350{,}000 $. ASIC cheaper by \$ 350,000 ✓ — consistent with "crossing at the origin, ASIC wins for all $N > 0$ ."

Recap

Recall Every cell in one sentence

Compare $N$ to $N^{*}$ : below → FPGA, above → ASIC, equal → tie; if the denominator is zero the lines never cross (compare start points); if the numerator is zero the lines cross at the origin (cheaper slope wins for all $N > 0$ ); if $N^{*}$ comes out negative there is no valid crossing (the cheaper-start, cheaper-slope option always wins); the numerator always uses the difference of NREs (which a re-spin can enlarge).

Which side of the crossing wins for volume below

N^{*}

FPGA — its steep line is still below the shallow ASIC line to the left of the crossing.

What does a zero denominator in

N^{*}

mean physically?

Equal per-unit costs → ASIC saves nothing per chip → lines are parallel → no crossing → compare start points instead.

What does a zero numerator (

N^{*} = 0

) mean?

Equal fixed costs (NREs) → lines cross at the origin → the option with the cheaper per-unit cost wins for every

N > 0

What does a negative

N^{*}

mean?

The crossing is at a negative (impossible) volume → no valid break-even → the cheaper-start, cheaper-slope option wins for all real

N

What goes in the numerator of

N^{*}

The difference

C_{N R E}^{A} - C_{N R E}^{F}

(the extra fixed cost of ASIC), not ASIC's NRE alone.

How does an ASIC re-spin change the graph?

It adds to

C_{N R E}^{A}

, shifting the crossing

N^{*}

rightward; the FPGA line is unchanged.

Prerequisites & neighbours: RTL Design & Verilog · Logic Synthesis · Lookup Tables (LUTs) & FPGA Architecture · Standard Cell Libraries · Static Timing Analysis · Place and Route · Non-Recurring Engineering (NRE) Cost · GDSII & Tape-out