3.5.8 · D5HDL & Digital Design Flow
Question bank — FPGA vs ASIC design flow
Prerequisite ideas you should already own before these bite: RTL Design & Verilog, Logic Synthesis, Lookup Tables (LUTs) & FPGA Architecture, Standard Cell Libraries, Static Timing Analysis, Place and Route, Non-Recurring Engineering (NRE) Cost, GDSII & Tape-out.
True or false — justify
FPGAs and ASICs use completely different design languages from the very first step.
False — both start from the same RTL (RTL Design & Verilog, Verilog/VHDL); the languages are identical and so is functional simulation. Only the back end differs.
Logic synthesis is unique to ASIC design.
False — both flows run Logic Synthesis to turn RTL into a gate netlist. What changes is the target library you synthesize to (LUT-friendly primitives vs standard cells).
An ASIC is always faster, smaller and lower-power than an FPGA running the same design.
True per chip — custom transistors beat generic ones. But this is a per-chip fact, not a per-project one: below the break-even volume the FPGA is cheaper overall, so "better" depends on volume and time-to-market.
The bitstream and the GDSII file are basically the same kind of output.
False — a bitstream configures existing hardware (LUT truth tables + routing switches); GDSII describes new geometry for a fab to etch. One programs a made chip, the other manufactures a chip.
Once you program an FPGA it keeps your design forever, like an ASIC.
False for the common SRAM-based FPGA — its config is volatile and reloads at every power-up (usually from a flash chip). ASIC logic is baked into transistors permanently.
Place and Route means the same thing on FPGA and ASIC.
Half-true — both place elements and route wires (Place and Route), but FPGA routing selects among pre-built switch-fabric wires, while ASIC routing creates new custom metal layers.
Static Timing Analysis only matters for ASICs.
False — Static Timing Analysis is run on both to confirm the clock period is met. The stakes differ: an FPGA missing timing is a recompile; an ASIC missing it after tape-out is a costly re-spin.
The NRE cost is paid per chip you manufacture.
False — NRE is the one-time fixed charge (masks, tooling, verification). That is exactly why it sits outside the term in .
An FPGA has essentially zero NRE.
Mostly true — you buy a pre-manufactured chip, so there are no mask costs. There is still engineering effort, but no fabrication NRE, which is why in the cost model.
Spot the error
"The flows diverge at RTL simulation because you simulate FPGAs and ASICs differently."
Wrong divergence point — RTL/functional simulation checks behavior and is identical for both. Divergence begins at technology mapping, where logic binds to real primitives.
"On an FPGA you fabricate new LUTs to hold your logic."
You don't fabricate anything — the LUTs already exist in silicon. You only fill their truth tables and select routing via the bitstream.
"Clock Tree Synthesis is a shared step in both back ends."
Error — CTS is ASIC-specific. It builds a balanced clock network because real custom-wire delay must be equalized; FPGA clock distribution trees are pre-built as dedicated global routing.
"DRC/LVS checks are needed for FPGAs before loading the bitstream."
No — Design-Rule and Layout-vs-Schematic checks guard fabricated geometry (an ASIC concern before tape-out). An FPGA has no new geometry to legalize.
"Break-even volume is where the FPGA becomes free."
Misread — is where total FPGA cost equals total ASIC cost. Neither is free there; it is the crossover after which the ASIC's up-front NRE has been repaid by cheaper units.
"A design bug found after tape-out is fixed the same way on both technologies."
False — on ASIC the silicon is the bug, so you need a mask re-spin (months, millions). On FPGA you recompile the bitstream and reload in minutes.
"Standard cells are just another name for LUTs."
No — standard cells are pre-characterized gate layouts (AND/OR/FF) that get physically fabricated on an ASIC. LUTs are generic reprogrammable memory tables already sitting on an FPGA.
Why questions
Why does the front end (spec → RTL → sim → synthesis) have to be shared?
Because both technologies implement the same behavioral intent; the divergence is only in how logic becomes physical, so all behavior-level work is reusable across both.
Why is the NRE placed outside the term in the cost model?
Because it is incurred once regardless of how many chips ship; only manufacturing scales with . Summing a one-time cost and a per-piece cost gives the straight line .
Why does going ASIC only pay off at high volume?
Its large NRE must be amortized over many units. The extra fixed cost divided by the per-unit saving () is exactly how many chips it takes to break even.
Why can an FPGA change its logic in seconds while an ASIC cannot?
The FPGA's silicon is generic and reused — only the SRAM configuration changes. An ASIC's silicon is the specific circuit, so changing logic means new masks.
Why does time-to-market favour FPGA even when ASIC is cheaper per chip?
FPGAs skip fabrication entirely — no mask making, no fab queue. You ship working hardware while the ASIC is still weeks from returning from the foundry.
Why must ASIC STA use real parasitics but FPGA STA can rely on the vendor's fixed fabric?
ASIC wires are freshly created, so their resistance/capacitance is only known after routing. FPGA routing resources are pre-built and pre-characterized by the vendor.
Edge cases
What happens at exactly the break-even volume ?
FPGA and ASIC total costs are equal, so cost alone doesn't decide — the tiebreaker becomes non-cost factors like update flexibility, time-to-market, or power.
What if (FPGA unit cost not higher)?
The denominator is zero or negative, so break-even is undefined or nonsensical — meaning ASIC never pays back and the FPGA wins at every volume.
What if the design might change monthly for years?
Even at high volume, favour FPGA (or delay ASIC) — each ASIC change is a full re-spin, so update frequency can outweigh per-chip savings entirely.
Is a flash-based or antifuse FPGA still volatile?
No — those retain configuration without power. The "volatile, reloads at power-up" trap applies specifically to SRAM-based FPGAs, the most common type.
What about very low volume, like a handful of prototypes?
FPGA dominates overwhelmingly — spending a million-dollar NRE to make ten chips is absurd; the near-zero-NRE FPGA wins with room to spare.
Can a design start on FPGA and later move to ASIC?
Yes, and it's common — the shared RTL front end means you validate on FPGA first, then re-target the same RTL through the ASIC back end once volume justifies the NRE.