FPGA vs ASIC design flow: Exercises — Hardware deep dive

The one formula you will keep reusing — memorise its meaning, not just its shape:

Level 1 — Recognition

Exercise 1.1

Name the four shared front-end steps of the FPGA and ASIC flows, in order.

Recall Solution

Specification — decide what the chip must do.
RTL design — write the behaviour in Verilog/VHDL (RTL Design & Verilog).
Functional / RTL simulation — check behaviour before any hardware detail.
Logic synthesis — turn RTL into a gate-level netlist (Logic Synthesis).

These are identical for both flows. Divergence begins at technology mapping, right after synthesis.

Exercise 1.2

For each output file, state whether it belongs to an FPGA or an ASIC flow, and in one line what it does: (a) Bitstream (b) GDSII

Recall Solution

(a) Bitstream → FPGA. It configures existing hardware: it fills every LUT truth table and sets every routing switch.
(b) GDSII → ASIC. It describes new geometry the foundry will etch into silicon (GDSII & Tape-out). One programs a chip that already exists; the other manufactures a new one.

Exercise 1.3

What is the atomic compute element that logic is mapped onto in (a) an FPGA and (b) an ASIC?

Recall Solution

(a) A LUT (Look-Up Table), alongside flip-flops, block RAM and DSP slices — all pre-built on the chip.
(b) Cells from a standard-cell library (AND/OR/flip-flop cells) that will be physically fabricated.

Level 2 — Application

Exercise 2.1

An FPGA has $C^{F}_{NRE}=\$ 0 $an d$ c^{F}{u}=$50 $. A n A S I C ha s$ C^{A}{NRE}=$2{,}000{,}000 $an d$ c^{A}_{u}=$8 $. C o m p u t e t h e b r e ak - e v e n v o l u m e$ N^{*}$.

Recall Solution

Plug into the formula: $N^{*} = \frac{C _{N R E}^{A} - C _{N R E}^{F}}{c _{u}^{F} - c _{u}^{A}} = \frac{2 , 000 , 000 - 0}{50 - 8} = \frac{2 , 000 , 000}{42} \approx 47, 619 units.$ Why this step? The numerator is the extra fixed cost of going ASIC ( $\$ 2\text{M} $); t h e d e n o mina t or i s t h e$ $42 $w es a v eo n e v er y c hi p . D i v i d in g t e l l s u s h o w man y c hi p s a r e n ee d e d t oe a r n t ha t$ $2\text{M}$ back.

Exercise 2.2

Using the numbers from 2.1, you plan to ship 20,000 units. Which technology is cheaper? Confirm by computing both total costs.

Recall Solution

Since $20, 000 < 47, 619 = N^{*}$ , we are below break-even → FPGA wins. Confirm with $C_{total} = C_{N R E} + N c_{u}$ :

FPGA: $0 + 20{,}000\times 50 = \$ 1{,}000{,}000$.
ASIC: $2{,}000{,}000 + 20{,}000\times 8 = 2{,}000{,}000 + 160{,}000 = \$ 2{,}160{,}000 $. F P G A ($ $1.0\text{M} $)$ < $A S I C ($ $2.16\text{M}$). ✓ The direction matches the break-even test.

Exercise 2.3

Same numbers, but now 200,000 units. Which wins? Confirm.

Recall Solution

$200, 000 > 47, 619 = N^{*}$ → ASIC wins.

FPGA: $0 + 200{,}000\times 50 = \$ 10{,}000{,}000$.
ASIC: $2{,}000{,}000 + 200{,}000\times 8 = 2{,}000{,}000 + 1{,}600{,}000 = \$ 3{,}600{,}000 $. A S I C ($ $3.6\text{M} $)$ < $F P G A ($ $10\text{M}$). ✓ Above break-even, the tiny per-unit cost of the ASIC pays off.

The picture below shows exactly what these two exercises mean — two straight lines crossing at $N^{*}$ .

Level 3 — Analysis

Exercise 3.1

A bug is discovered after the chip is manufactured. Explain, step by step, why fixing it costs millions and months on an ASIC but minutes on an FPGA.

Recall Solution

ASIC: the silicon is your circuit. Fixing the bug means editing the RTL, re-running synthesis, Place and Route, STA, DRC/LVS, generating new masks, and paying the full $C_{N R E}$ again — a "re-spin". Fabrication takes weeks-to-months. Cost ≈ another full NRE.
FPGA: the silicon is generic and reused. Only the configuration was wrong. Recompile the RTL to a new bitstream and reload it into the SRAM cells — minutes, near-zero cost. The root cause: on an ASIC the bug is etched into transistors; on an FPGA the bug lives only in reprogrammable switch settings.

Exercise 3.2

STA and Place and Route appear on both flows in spirit, but Clock Tree Synthesis (CTS) is listed only for the ASIC. Why is CTS an ASIC-specific step?

Recall Solution

CTS builds a balanced clock-distribution network so the clock edge reaches every flip-flop at nearly the same instant. On an ASIC the clock wires are created from scratch out of custom metal, so their delays are unknown until you design them — you must synthesize and balance the tree yourself. On an FPGA the clock network is a pre-built, pre-balanced global resource baked into the silicon; you simply use it. No wires to create means no tree to synthesize.

Exercise 3.3

Why does an SRAM-based FPGA usually sit next to a small flash memory chip on the board, while an ASIC needs none?

Recall Solution

SRAM is volatile — it forgets its contents at power-off. The FPGA's configuration lives in SRAM cells, so on every power-up the bitstream must be reloaded, typically from an adjacent non-volatile flash chip that stores it permanently. An ASIC's "configuration" is the physical transistors and wiring — it is baked in forever and cannot be lost, so no external config memory is required.

Level 4 — Synthesis

Exercise 4.1

You are told: FPGA $C^{F}_{NRE}=\$ 0 $,$ c^{F}{u}=$40 $; A S I C$ C^{A}{NRE}=$1{,}500{,}000 $,$ c^{A}_{u}=$6$. Your startup will ship 30,000 units in year one but expects the product spec to change twice before shipping. Argue which technology to choose — using both the cost model and a non-cost factor.

Recall Solution

Cost view: break-even is $N^{*} = \frac{1 , 500 , 000 - 0}{40 - 6} = \frac{1 , 500 , 000}{34} \approx 44, 118 units.$ $30, 000 < 44, 118$ → cost model already favours FPGA. Non-cost view: the spec will change twice. On an ASIC each change is a re-spin (new masks, months, ≈ a fresh NRE); on an FPGA each change is a bitstream recompile. So both the numbers and the update-frequency point the same way. Decision: FPGA — below break-even and the design is not yet frozen. Migrate to ASIC only once volume climbs past $N^{*}$ and the spec stabilises.

Exercise 4.2

Derive an expression for the total saving an ASIC gives over an FPGA at a volume $N$ (assume $N > N^{*}$ ). Then evaluate it for the numbers in 4.1 at $N = 100, 000$ .

Recall Solution

Derivation. Saving = FPGA cost − ASIC cost: $S (N) = (C_{N R E}^{F} + N c_{u}^{F}) - (C_{N R E}^{A} + N c_{u}^{A}) .$ Group the fixed terms and the per-unit terms: $S (N) = (C_{N R E}^{F} - C_{N R E}^{A}) + N (c_{u}^{F} - c_{u}^{A}) .$ Why this shape: you lose the extra ASIC fixed cost up front (first bracket is negative), but gain the per-unit saving on every chip (second term grows with $N$ ). The two balance exactly at $N^{*}$ . Evaluate at $N = 100, 000$ : $S = (0 - 1, 500, 000) + 100, 000 \times (40 - 6) = - 1, 500, 000 + 3, 400, 000 = $1, 900, 000.$ The ASIC saves $1.9 M at 100,000 units.

Level 5 — Mastery

Exercise 5.1

A company will ship exactly $N^{*}$ units — precisely at break-even — with FPGA $C^{F}_{NRE}=\$ 0 $,$ c^{F}{u}=$40 $, A S I C$ C^{A}{NRE}=$1{,}400{,}000 $,$ c^{A}_{u}=$5 $. (a) F in d$ N^{*}$. (b) Show the two total costs are equal there. (c) Given they are equal, which should they still pick, and why?

Recall Solution

(a) $N^{*} = \frac{1 , 400 , 000 - 0}{40 - 5} = \frac{1 , 400 , 000}{35} = 40, 000$ units. (b) Check both costs at $N = 40, 000$ :

FPGA: $0 + 40{,}000\times40 = \$ 1{,}600{,}000$.
ASIC: $1{,}400{,}000 + 40{,}000\times5 = 1{,}400{,}000+200{,}000 = \$ 1{,}600{,}000 $. E q u a l ✓ . * * (c) * * W i t h cos tt i e d, t h e * t i e - b r e ak er s * d ec i d e : * * F P G A * * i f t h es p ec mi g h t s t i l l c han g eor t im e - t o - ma r k e t i s t i g h t (n or e - s p in r i s k, n o f ab l e a d t im e); * * A S I C * * i f v o l u m e i se x p ec t e d t o * g r o w p a s t *$ 40{,}000$ next year, since above break-even the ASIC pulls ahead and the NRE is already "paid for" in the plan. So the honest answer is: at exact break-even, lean FPGA unless you are confident volume will climb.

Exercise 5.2

Two ASIC vendors bid on the same job. Vendor A: $C_{NRE}=\$ 3\text{M} $,$ c_{u}=$4 $. V e n d or B :$ C_{NRE}=$1\text{M} $,$ c_{u}=$9$. At what volume does the cheaper-mask, pricier-chip Vendor B stop being the better deal? Interpret.

Recall Solution

Set the two ASIC total costs equal and solve for $N$ (identical algebra to the FPGA-vs-ASIC break-even, just two ASICs): $C_{N R E}^{B} + N c_{u}^{B} = C_{N R E}^{A} + N c_{u}^{A} \Rightarrow N = \frac{C _{N R E}^{A} - C _{N R E}^{B}}{c _{u}^{B} - c _{u}^{A}} = \frac{3 , 000 , 000 - 1 , 000 , 000}{9 - 4} = \frac{2 , 000 , 000}{5} = 400, 000.$ Interpretation: below 400,000 units, Vendor B (cheap masks, expensive chips) wins because the extra $\$ 2\text{M} $o f V e n d or A^{'} s ma s k cos t ha s n^{'} t b ee n r eco v er e d . A b o v e 400, 000, * * V e n d or A * *^{'} s$ $5$-per-chip saving overtakes. The break-even formula is general — it compares any two "fixed + per-unit" cost lines, not just FPGA-vs-ASIC.

Exercise 5.3

Sketch (describe) the full decision as a flow: given a project, what questions in what order lead you to FPGA vs ASIC? Include volume, spec stability, and time-to-market.

Recall Solution

A clean decision order:

Is the spec frozen? If it may still change → FPGA (re-spins are ruinous). If frozen → continue.
Is time-to-market urgent? If you must ship now → FPGA (fab lead time is months). Else → continue.
Is expected volume $> N^{*}$ ? Compute $N^{*} = \frac{C _{N R E}^{A} - C _{N R E}^{F}}{c _{u}^{F} - c _{u}^{A}}$ . If yes → ASIC (per-unit saving pays back the NRE). If no → FPGA. The diagram below captures this ordering.

Rapid self-test

Break-even $N^{*}$ with $C^{A}_{NRE}=\$ 2\text{M} $,$ C^{F}{NRE}=0 $,$ c^{F}{u}=$50 $,$ c^{A}_{u}=$8 $? :::$ 2{,}000{,}000/42\approx 47{,}619 $u ni t s . A t 20, 000 u ni t s (n u mb er s ab o v e), w hi c hi sc h e a p er an d b y h o w m u c h ? ::: F P G A;$ $1.0\text{M} $v s$ $2.16\text{M} $, a$ $1.16\text{M}$ saving.

Why is CTS ASIC-specific?

FPGA clock trees are pre-built and balanced; ASIC clock wires are created from scratch and must be balanced by synthesis.

The break-even formula secretly answers what general question?

Where do two "fixed cost + per-unit cost" straight lines cross?