FPGA vs ASIC design flow

3.5.8 · Hardware › HDL & Digital Design Flow

DO flows exist kyon karte hain bilkul bhi?

KYA chahiye hame: ek digital system ke behavioral description ko ek kaam karne wale physical chip mein badalna.

KYO split hai: yahan ek gehri engineering trade-off hai flexibility aur efficiency ke beech.

Agar tum apne design ke liye exact transistors banao (ASIC), tum sabse chhoti, sabse tez, sabse kam power wali chip paate ho — lekin tum ek bahut bada one-time cost chukate ho (masks, fabrication) aur ise bana lene ke baad badal nahi sakte.
Agar tum ek generic reprogrammable chip (FPGA) use karo, tum design ko seconds mein badal sakte ho aur up front almost kuch nahi chukate — lekin generic-ness ka tumhe area, speed, aur power mein nuksan hota hai.

Shared front end

Common early steps (dono ke liye identical):

Specification — chip ko kya karna chahiye.
RTL design — Verilog/VHDL likho.
Functional / RTL simulation — kisi bhi hardware detail se pehle behavior verify karo.
Logic synthesis — RTL ko gates ke netlist mein translate karo.

Divergence synthesis pe shuru hoti hai, kyunki jis cheez mein synthesize karte ho woh alag hoti hai.

Jahan flows split hoti hain

FPGA-specific back end

Step	KYA karta hai	KYO zaroori hai
Technology mapping	Logic ko LUTs mein pack karo	LUTs atomic compute unit hain
Place	Har LUT/FF ko ek physical tile assign karo	Chip ka fixed tile grid hota hai
Route	Tiles ko programmable switch fabric se connect karo	Wires pre-built hain lekin select karni padti hain
Bitstream generation	Config bits produce karo	Bits har LUT truth-table & switch set karte hain
Configure/Program	Bitstream ko SRAM cells mein load karo	Chip tumhara circuit "ban jaati" hai; power-off pe erase ho jaati hai

ASIC-specific back end

Step	KYA karta hai	KYO zaroori hai
Floorplanning	Chip regions allocate karo	Physical area create ki ja rahi hai
Place & Route	Standard cells ko position aur wire karo	Custom metal layers
Clock Tree Synthesis (CTS)	Balanced clock network banao	Real wire delay ko equalize karna hoga
Static Timing Analysis (STA)	Real parasitics ke saath timing verify karo	Re-spin allowed nahi hai
DRC / LVS	Design-Rule & Layout-vs-Schematic checks	Fab illegal geometry reject kar dega
GDSII → Tape-out → Fab	Masks foundry ko bhejo	Silicon physically etch karo

Common mistakes (steel-manned)

Flashcards

Kis step par FPGA aur ASIC flows pehli baar diverge karti hain?

Technology mapping / physical implementation par — front end (spec, RTL, simulation, synthesis) shared hai.

FPGA par map kiya jaane wala atomic compute element kya hai?

Ek LUT (Look-Up Table), plus flip-flops, block RAM, DSP slices.

ASIC logic ko LUTs ki jagah kis cheez mein map karta hai?

Ek standard-cell library mein jo physically fabricate ki jaayegi.

FPGA back end ka final output kya hai?

Ek bitstream jo LUT contents aur routing switches configure karta hai.

ASIC back end ka final output kya hai?

GDSII masks jo foundry ko bheji jaati hain (tape-out).

Total cost model likho.

C_{t o t a l} (N) = C_{N R E} + N c_{u ni t}

Break-even volume formula derive karo.

FPGA cost = ASIC cost set karo, N ke liye solve karo:

N^{*} = (C_{N R E}^{A} - C_{N R E}^{F}) / (c_{u}^{F} - c_{u}^{A})

Post-fab bug ASIC ke liye catastrophic kyon hai lekin FPGA ke liye cheap?

ASIC ko mehenga mask re-spin chahiye; FPGA minutes mein sirf nayi bitstream reload karta hai.

CTS (Clock Tree Synthesis) kya karta hai, aur yeh ASIC-specific kyon hai?

Real wire delay equalize karne ke liye ek balanced clock distribution network banata hai; FPGA clock trees pre-built hote hain.

Bitstream aur GDSII mein fark?

Bitstream existing hardware configure karta hai; GDSII nayi geometry describe karta hai manufacture karne ke liye.

Zyattar FPGAs volatile kyon hote hain?

Woh bitstream SRAM mein store karte hain, jo power-off par config lose kar deta hai (flash se reload karna padta hai).

Break-even volume se neeche, kaun si technology jeeтti hai aur kyon?

FPGA — ASIC ki badi NRE, low volume par per-unit savings se recover nahi hoti.

Recall Feynman: ek 12-saal ke bacche ko samjhao

Socho tumne ek Lego robot invent kiya. Ek real banana ke tumhare paas do tarike hain. Tarika 1 (FPGA): ek magic box khareed lo jo pehle se chhoti switches se bhari ho. Tum bas switches flip karo taaki box pretend kare ki woh tumhara robot hai. Agar galti ho, dobara flip karo — ek minute mein done. Box thoda chunky aur slow hai, aur unplug karne par sab bhool jaata hai. Tarika 2 (ASIC): apna blueprint ek factory ko bhejo jo sand pighalaakar exact robot chip banaye. Woh chhoti hai, super fast hai, kam power peeti hai — lekin set up karna bahut mehenga hai aur agar blueprint mein typo thi, toh ise phenk do aur dobara pay karo. Dono robot ki same drawing se shuru hote hain. Sirf drawing kaise real cheez banti hai mein fark hai.

Connections

RTL Design & Verilog — shared source jo dono flows synthesize karti hain.
Logic Synthesis — gate-level netlist jo dono back ends ko feed karta hai.
Lookup Tables (LUTs) & FPGA Architecture — FPGA mapping target.
Standard Cell Libraries — ASIC mapping target.
Static Timing Analysis — ASIC back end mein critical.
Place and Route — shared concept, alag physical meaning.
Non-Recurring Engineering (NRE) Cost — volume decision drive karta hai.
GDSII & Tape-out — fab ko ASIC hand-off.