Level 1 — RecognitionHDL & Digital Design Flow

HDL & Digital Design Flow

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Level: 1 (Recognition) Time Limit: 20 minutes Total Marks: 30

Section A — Multiple Choice (1 mark each, 10 marks)

Choose the single best answer.

Q1. In Verilog, which keyword is used to describe combinational logic sensitive to all inputs automatically?

(a) always @(posedge clk)
(b) always @(*)
(c) initial
(d) assign delay

Q2. Which assignment operator is used for non-blocking assignments in Verilog?

(a) =
(b) <=
(c) :=
(d) ==

Q3. A gate-level netlist is produced by which stage of the design flow?

(a) Simulation
(b) Testbench writing
(c) Synthesis
(d) Place & route only

Q4. In static timing analysis, the setup time requirement checks that data arrives:

(a) After the next clock edge
(b) Before the capturing clock edge with margin
(c) Only during reset
(d) Independent of the clock

Q5. The critical path in a synchronous circuit is:

(a) The shortest combinational path
(b) The longest register-to-register delay path that limits clock frequency
(c) The clock net itself
(d) The reset path

Q6. Which is a primary advantage of an FPGA over an ASIC?

(a) Lower unit cost at very high volume
(b) Reconfigurability and faster time to market
(c) Higher maximum clock speed always
(d) Lower power always

Q7. In VHDL, a signal is declared with which keyword?

(a) reg
(b) wire
(c) signal
(d) logic

Q8. A testbench in HDL is used primarily to:

(a) Synthesize the design into gates
(b) Provide stimulus and check the DUT's responses in simulation
(c) Generate the physical layout
(d) Program the FPGA fuses

Q9. RTL (Register Transfer Level) describes a design in terms of:

(a) Transistor sizing
(b) Data flow between registers and the logic operations on that data
(c) Physical wire routing
(d) Package pinout only

Q10. If the critical path delay is 8 ns (including setup), the maximum clock frequency is approximately:

(a) 8 GHz
(b) 125 MHz
(c) 12.5 MHz
(d) 800 MHz

Section B — Matching (5 marks)

Q11. Match each term in Column X to its correct description in Column Y. (1 mark each)

Column X	Column Y
1. Blocking assignment (`=`)	A. Updated at end of time step; models flip-flops
2. Non-blocking assignment (`<=`)	B. Executes sequentially, updates immediately
3. `assign` statement	C. Continuous drive for combinational `wire`
4. `always @(posedge clk)`	D. Programmable logic, reconfigurable
5. FPGA	E. Models synchronous sequential logic

Section C — True/False with Justification (3 marks each, 15 marks)

State True or False and give a one-line justification for each. (1 mark T/F, 2 marks justification)

Q12. Using blocking assignments (=) inside a clocked always block for pipeline registers is the recommended coding style.

Q13. Synthesis converts an RTL description directly into a physical GDSII layout ready for fabrication.

Q14. In an ASIC flow, once the chip is fabricated, the logic function cannot be changed without a new mask set.

Q15. Reducing the number of logic levels on the critical path can increase the maximum operating clock frequency.

Answer keyMark scheme & solutions

Section A (1 mark each)

Q1 — (b) always @(*) auto-builds the sensitivity list of all read signals, the standard combinational construct. (a) is sequential; (c) is non-synthesizable initialization.

Q2 — (b) <= is the non-blocking operator (RHS evaluated, LHS updated at end of time step). = is blocking.

Q3 — (c) Synthesis maps RTL to a gate-level netlist using a target library.

Q4 — (b) Setup checks data is stable before the capturing edge by at least the setup time; violation → metastability.

Q5 — (b) The longest reg-to-reg path sets the minimum clock period and thus max frequency.

Q6 — (b) FPGAs are reconfigurable with fast time-to-market; ASICs win at high volume/power.

Q7 — (c) VHDL uses signal; reg/wire/logic belong to Verilog/SystemVerilog.

Q8 — (b) A testbench applies stimulus to the DUT and checks outputs in simulation; it is non-synthesizable.

Q9 — (b) RTL abstracts the design as registers plus combinational logic transferring data between them.

Q10 — (b) $f_{max} = 1/T = 1/(8\text{ ns}) = 1.25\times10^{8}\,\text{Hz} = 125\text{ MHz}$ .

Section B (1 mark each)

Q11.

1 → B (blocking = immediate, sequential)
2 → A (non-blocking = end-of-step update, flip-flops)
3 → C (assign continuous drive of a wire)
4 → E (posedge clk models synchronous logic)
5 → D (FPGA = programmable/reconfigurable)

Section C (1 T/F + 2 justification)

Q12 — False. Non-blocking (<=) must be used for clocked/sequential logic to correctly model concurrent flip-flop updates and avoid race conditions; blocking is used for combinational blocks.

Q13 — False. Synthesis produces a gate-level netlist; physical layout (GDSII) is produced later by place-and-route in the physical design stage.

Q14 — True. ASIC logic is fixed in silicon by the mask set; changing function requires a costly re-spin with new masks.

Q15 — True. $f_{max}=1/t_{path}$ ; fewer logic levels shortens the critical path delay, lowering the minimum period and raising $f_{max}$ .

[
  {"claim":"8 ns critical path gives 125 MHz max clock", "code":"T=8e-9\nf=1/T\nresult = abs(f-125e6) < 1"},
  {"claim":"Non-blocking is correct for sequential, blocking for combinational (encoded check)", "code":"seq_uses_nonblocking=True\ncomb_uses_blocking=True\nresult = seq_uses_nonblocking and comb_uses_blocking"},
  {"claim":"Reducing period by fewer logic levels raises fmax: 8ns->5ns increases frequency", "code":"f1=1/8e-9\nf2=1/5e-9\nresult = f2 > f1"},
  {"claim":"fmax for 5 ns path is 200 MHz", "code":"result = abs(1/5e-9 - 200e6) < 1"}
]