Single-cycle datapath design
WHAT is a single-cycle datapath?
The building blocks (using the classic MIPS-style RISC example):
| Block | WHAT it does |
|---|---|
| PC (Program Counter) | Holds address of current instruction |
| Instruction Memory | Reads the instruction at address PC |
| Register File | 2 read ports + 1 write port for register operands |
| ALU | Arithmetic/logic + address computation + branch compare |
| Data Memory | Load/store access to memory |
| Sign-extender | Turns a 16-bit immediate into 32 bits |
| Muxes | Select between alternative data sources |
| Adders | Compute PC+4 and branch target |
HOW the data flows (5 conceptual stages, all one cycle)
Even though it's single-cycle, we can name the logical stages the signal passes through:
- Fetch (IF): Instruction ← InstrMem[PC]; compute PC+4.
- Decode / Register read (ID): Read
rs,rt; sign-extend immediate; generate control. - Execute (EX): ALU does arithmetic or computes address / branch decision.
- Memory (MEM): Load reads Data Mem; store writes it. (R-type does nothing here.)
- Write-back (WB): Result written to register file.
WHY do we need each mux? (The heart of the design)
- ALUSrc mux — R-type wants the ALU's 2nd input to be a register (
rt); load/store/immediate want the sign-extended immediate. They disagree → mux. - MemToReg mux — R-type writes back the ALU result; load writes back memory data. Disagree → mux.
- RegDst mux — R-type destination field is
rd(bits 15–11); I-type destination isrt(bits 20–16). Disagree → mux. - PCSrc mux — normally next PC = PC+4; a taken branch wants the branch target. Disagree → mux, controlled by
Branch AND Zero.
Control signals — derive them, don't memorize
The opcode selects a row in a truth table. Ask for each signal: "what does THIS instruction need?"
| Signal | R-type (add) |
lw |
sw |
beq |
|---|---|---|---|---|
| RegWrite | 1 | 1 | 0 | 0 |
| ALUSrc (use imm?) | 0 | 1 | 1 | 0 |
| MemRead | 0 | 1 | 0 | 0 |
| MemWrite | 0 | 0 | 1 | 0 |
| MemToReg | 0 | 1 | X | X |
| RegDst (=rd?) | 1 | 0 | X | X |
| Branch | 0 | 0 | 0 | 1 |
| ALUOp | funct | add | add | sub |
WHY single-cycle is slow: the clock period
Forecast-then-Verify
Recall Forecast: what happens to a single-cycle CPU if we add a
mul instruction whose ALU stage needs 500 ps instead of 200 ps?
Verify: The new lw-style critical path might not change, but the mul path becomes ps. Since clock = max over all instructions, rises from 800 → 900 ps for EVERY instruction. One slow instruction penalizes all — the fundamental flaw of single-cycle.
Common mistakes
Active-recall flashcards
#flashcards/hardware
Single-cycle datapath: how many cycles per instruction?
What determines the single-cycle clock period?
Which instruction is usually the critical path in MIPS single-cycle, and why?
lw, because it passes through all five stages including both memories.What does the ALUSrc mux choose between?
rt value vs. sign-extended immediate.What does MemToReg mux choose between?
What does RegDst mux choose between?
rd (R-type) vs. rt (I-type).Formula for branch target address?
Why shift the branch immediate left by 2?
What controls the PCSrc mux for a taken branch?
Why does sw set RegWrite = 0?
Why is a fast add still slow in single-cycle?
Why do PC+4 and branch target need separate adders (not the ALU)?
Recall Feynman: explain to a 12-year-old
Imagine a factory where a toy must go through 5 machines in a row: unpack → read instructions → build → paint → wrap. In a single-cycle factory, you demand that ONE whole toy finishes in ONE ring of the bell. So the bell can only ring as fast as the toy that needs all five machines and the slowest paint. Even a toy that skips painting still has to wait for the same slow bell. It's simple to build (each machine has its own tools, nobody shares) but wasteful — everyone waits for the slowpoke.
Connections
- Pipelining — fixes single-cycle's wasted time by overlapping stages.
- Multi-cycle datapath — reuses one ALU across cycles; different tradeoff.
- Control unit design — how the opcode → control-signal truth table is built.
- ALU design — the block on the critical path.
- Performance equation — CPI × clock period × instruction count.
- Memory hierarchy — instruction/data memory access times dominate the period.
Concept Map
Hinglish (regional understanding)
Intuition Hinglish mein samjho
Single-cycle datapath ka matlab hai: ek poori instruction ek hi clock cycle mein complete ho jaati hai, yaani CPI = 1. Hardware blocks — PC, Instruction Memory, Register File, ALU, Data Memory — sab ek line mein jude hote hain, aur data ek hi tick mein fetch se lekar write-back tak flow karta hai. Har instruction ke liye alag wire aur alag block hota hai, kuch bhi reuse nahi hota ek cycle ke andar.
Sabse important concept hai mux (multiplexer). Mux wahan aata hai jahan alag-alag instructions ko ek hi block mein alag input chahiye. Jaise ALUSrc mux — R-type ko register value chahiye, lekin lw/sw ko sign-extended immediate. Dono "disagree" karte hain, isliye mux lagate hain jo control signal se decide karta hai kaunsa input jayega. Isi tarah MemToReg (ALU result vs memory data), RegDst (rd vs rt), aur PCSrc (PC+4 vs branch target) — sab muxes disagreement solve karte hain.
Ab problem: single-cycle mein clock period sabse slow instruction ke barabar hona chahiye. MIPS mein lw sabse slow hai kyunki wo saare 5 stages touch karta hai (dono memories). Maan lo lw ko 800 ps lagta hai aur add ko sirf 600 ps — phir bhi clock 800 ps ka hi hoga, kyunki sabko same bell ka wait karna padta hai. Isi wajah se fast add bhi 200 ps waste karta hai har baar. Yahi single-cycle ki badi kamzori hai — aur isi ko pipelining aage jaake theek karta hai. Yaad rakho: CPI=1 achha lagta hai, lekin clock period bahut bada hone se overall performance slow ho jaati hai.