Level 1 — RecognitionProcessor Datapath & Pipelining

Processor Datapath & Pipelining

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Difficulty Level: 1 (Recognition — MCQ / Matching / True-False with justification) Time Limit: 20 minutes Total Marks: 30

Section A — Multiple Choice (1 mark each, 10 marks)

Choose the single best answer.

Q1. In a classic 5-stage pipeline, the stages in order are:

(a) IF – EX – ID – MEM – WB
(b) IF – ID – EX – MEM – WB
(c) ID – IF – EX – WB – MEM
(d) IF – ID – MEM – EX – WB

Q2. A structural hazard occurs when:

(a) An instruction depends on the result of a previous instruction
(b) Two instructions need the same hardware resource in the same cycle
(c) A branch outcome is unknown
(d) An exception is raised mid-instruction

Q3. The primary purpose of pipeline registers (e.g., IF/ID, ID/EX) is to:

(a) Increase clock frequency directly
(b) Store the entire register file
(c) Hold intermediate data and control signals between stages
(d) Eliminate data hazards permanently

Q4. Forwarding (bypassing) is used to resolve:

(a) Structural hazards
(b) Control hazards only
(c) Data hazards without always stalling
(d) Exceptions

Q5. The load-use hazard requires at least how many stall cycle(s) even with forwarding, in the classic 5-stage pipeline?

(a) 0
(b) 1
(c) 2
(d) 3

Q6. In a single-cycle datapath, the clock period is determined by:

(a) The average instruction latency
(b) The fastest instruction
(c) The slowest (critical-path) instruction
(d) The number of pipeline stages

Q7. The ideal (steady-state) CPI of a scalar pipeline with no hazards is:

(a) 0
(b) 1
(c) equal to the number of stages
(d) 0.2

Q8. A control hazard is typically caused by:

(a) A load followed immediately by a use
(b) A branch or jump changing the instruction flow
(c) Two ALU operations back to back
(d) A single memory port

Q9. A "precise exception" means:

(a) The exception is handled in exactly one cycle
(b) Instructions before the faulting one complete; those after do not affect state
(c) The pipeline never flushes
(d) The exception cause register is optional

Q10. A disadvantage of very deep pipelining is:

(a) Lower clock frequency
(b) Greater penalty per hazard/flush and more register overhead
(c) Impossibility of forwarding
(d) Reduced instruction count

Section B — Matching (1 mark each, 6 marks)

Q11. Match each pipeline stage/component (I–VI) to its function (A–F).

#	Item
I	IF stage
II	ID stage
III	EX stage
IV	MEM stage
V	WB stage
VI	Hazard detection unit

Key	Function
A	Writes result back to register file
B	Fetches instruction from memory
C	Performs ALU computation / address calc
D	Decodes instruction and reads registers
E	Detects load-use hazards and inserts stalls
F	Accesses data memory (load/store)

Section C — True / False with Justification (2 marks each, 14 marks)

1 mark for correct T/F, 1 mark for correct justification.

Q12. Pipelining reduces the latency of a single instruction. (T/F + justify)

Q13. Forwarding can resolve every data hazard without any stall. (T/F + justify)

Q14. A multi-cycle datapath allows different instructions to take different numbers of clock cycles. (T/F + justify)

Q15. Increasing pipeline depth always increases throughput proportionally. (T/F + justify)

Q16. Duplicating memory (separate instruction and data caches) can eliminate a common structural hazard. (T/F + justify)

Q17. A taken branch resolved in the MEM stage causes a larger flush penalty than one resolved in the ID stage. (T/F + justify)

Q18. In a single-cycle machine every instruction, including simple ones, is limited by the critical path of the slowest instruction. (T/F + justify)

Answer keyMark scheme & solutions

Section A (10 marks)

Q1 — (b) IF–ID–EX–MEM–WB. This is the canonical MIPS-style order. (1)

Q2 — (b) Structural hazard = resource conflict in the same cycle (e.g., single memory port used by IF and MEM). (1)

Q3 — (c) Pipeline registers latch data + control signals so each stage works on a different instruction each cycle. (1)

Q4 — (c) Forwarding routes a result from EX/MEM or MEM/WB back to a dependent instruction's inputs, avoiding stalls. (1)

Q5 — (b) 1 stall. Load data is available only after MEM; a dependent instruction in EX the next cycle still needs one bubble even with forwarding. (1)

Q6 — (c) Single-cycle clock = worst-case (slowest instruction) path since every instruction completes in one cycle. (1)

Q7 — (b) Ideal steady-state CPI = 1 (one instruction completes per cycle). (1)

Q8 — (b) Control hazards arise from branches/jumps altering the PC. (1)

Q9 — (b) Precise exceptions: architectural state reflects all prior instructions and none after. (1)

Q10 — (b) Deeper pipes suffer larger flush penalties and more latch/register overhead. (1)

Section B (6 marks)

Q11 — I→B, II→D, III→C, IV→F, V→A, VI→E. (1 mark each, 6 total)

Section C (14 marks)

Q12 — False. Pipelining improves throughput, not single-instruction latency (latency may even rise slightly due to register overhead). (T/F 1 + justify 1)

Q13 — False. The load-use case still needs one stall because load data isn't ready in time to be forwarded. (1+1)

Q14 — True. Multi-cycle datapaths break execution into steps; simple instructions use fewer cycles than complex ones. (1+1)

Q15 — False. Diminishing returns: register overhead, hazard penalties, and clock-skew limits mean throughput does not scale linearly. (1+1)

Q16 — True. Splitting instruction and data memory removes the IF vs MEM port conflict, the classic structural hazard. (1+1)

Q17 — True. Resolving later (MEM) flushes more already-fetched instructions than resolving in ID, so penalty is larger. (1+1)

Q18 — True. Since all instructions share one fixed clock period set by the slowest path, simple instructions waste time. (1+1)

Sample numeric elaboration (for grading discussion)

Q5/Q13: load-use penalty = 1 cycle.
Q17: branch in MEM (stage 4) flushes 3 instructions; branch in ID (stage 2) flushes 1.
Q7: ideal CPI = 1.

[
  {"claim":"Load-use stall in classic 5-stage pipeline is 1 cycle","code":"load_result_stage=4\ndependent_needs_stage=3\nnext_cycle_use=3\nstall = 1 if load_result_stage - dependent_needs_stage > 0 else 0\nresult = (stall == 1)"},
  {"claim":"Ideal steady-state pipeline CPI equals 1","code":"instructions=100\ncycles = instructions - 1 + 5\ncpi_ideal_limit = 1\nresult = (cpi_ideal_limit == 1)"},
  {"claim":"Branch resolved in MEM flushes more instructions than in ID","code":"flush_mem = 4 - 1\nflush_id = 2 - 1\nresult = (flush_mem > flush_id) and (flush_mem == 3) and (flush_id == 1)"}
]