Before you can read the single-cycle datapath note you must own every symbol it throws at you. Below, each idea is built from nothing, given a picture, and justified by the one question it answers. Read top to bottom — each rung of the ladder needs the one below it.
Put 32 wires side by side and you can spell a number. We must agree which wire counts for how much.
Figure 1 — read this: eight little boxes on top are single-bit wires labelled with their place values; the fat red arrow below is the same information carried as one 32-bit bus. Learn that "one fat arrow with a slash and a 32 = thirty-two wires travelling together."
Why the topic needs it: every box in the datapath — the ALU, the memories, the register file — speaks in 32-bit words. When the parent note draws one arrow into the ALU, that arrow is really 32 wires.
The register file in the parent note has two read ports and one write port:
A read port = a lookup: "here is a 5-bit register number, hand me its 32-bit value." Two ports let us read two operands at once (like add needing two inputs).
A write port = a store: "here is a register number and a value; on the next bell, put the value there." It only acts when the RegWrite control wire is 1.
Figure 2 — read this: two black arrows on the left (rs, rt) go in, two black arrows on the right (read data 1, read data 2) come out — those are the two read ports. The red arrow at the bottom is the single write port, and it only moves data when RegWrite = 1. Learn: reading is always allowed; writing needs permission.
Why the topic needs it:rs, rt, rd, RegWrite, and the "write-back" stage all live or die by this shelf.
Figure 3 — read this: each small black box is one byte-mailbox with its own address number underneath. The red outline groups four consecutive bytes into one instruction word. Learn: memory is numbered per byte, but we grab things four bytes at a time.
The parent note has two separate memories:
Instruction memory — read-only during running; you hand it PC, it hands back the instruction word there.
Data memory — read and write; used only by lw (load word) and sw (store word).
Why the topic needs it: the MEM stage, MemRead, MemWrite, and the load/store instructions are all conversations with these mailboxes.
The straight-ahead choice PC + 4 (run the next instruction in line).
The branch choice — a conditional redirect if a compare succeeds (see Branch in §8).
The jump choice — an unconditional redirect (see J-type in §5).
A little box called an adder (see §7) computes PC + 4 while the rest of the instruction executes. On the next bell, the chosen value loads into the PC.
Why the topic needs it: the entire Fetch stage is "read instruction at PC, then decide the next PC."
An instruction is a 32-bit word chopped into labelled slots. You do not compute these — you just read off which bits mean what. MIPS uses three carvings: R-type, I-type, and J-type.
Figure 4 — read this: three strips share the same 6-bit redopcode slot. The top (R-type) ends in rd+funct; the middle (I-type) ends in a 16-bit immediate; the bottom (J-type) has one wide 26-bit jump target. Learn: same 32 bits, three different carvings.
Why the topic needs it: every mux in the note (defined in §8) exists because different instruction types pull their operands from different fields of this same 32-bit word — and the jump target is the field that feeds the PC directly.
The immediate is only 16 bits, but the ALU works on 32-bit words. We must grow it to 32 bits — but how we fill the new high bits depends on the instruction.
Why the topic needs it: the branch-target formula (PC+4)+(SignExt(imm)≪2) uses sign-extension then shift; the jump uses the same "×4" shift on its 26-bit target; and andi/ori need the zero-extension path instead.
Figure 5 — read this: two black arrows enter the red mux on the left; only one leaves on the right. The arrow coming up from the bottom is the select control wire that decides which input wins. Learn: a mux is a controllable one-of-many switch, not a calculator.
Why the topic needs it: these five names appear all over the parent note's control table; here they are defined once, from the mux idea.
The diagram is a dependency ladder: each arrow means "you must understand the box at the tail before the box at the head makes sense." Follow arrows in the direction they point. Everything on the left/top is raw material; all paths funnel into the single node "Single-cycle datapath" at the bottom — that is the note you are preparing for. If any incoming arrow to a box points from something you can't yet explain, go back and re-read that earlier section.
Why the topic needs it: the whole "single-cycle is slow" argument, the Performance equation, and the motivation for Pipelining rest on this one inequality.
