Let each stage take t time. A single non-pipelined instruction takes all k stages:
Tinstr=k⋅t
Non-pipelined, n instructions run one after another:
Tseq=n⋅k⋅t
Pipelined: the clock period must fit the slowest stage, so cycle time =t (assuming balanced stages). The first instruction needs k cycles to fill the pipe. After that, one instruction finishes every cycle. So instructions 2,3,…,n add one cycle each:
Tpipe=fillk⋅t+remaining(n−1)⋅t=(k+n−1)t
In reality stages are unbalanced and registers add latency treg:
tclk=max(stage delays)+treg
This is why we try to balance stages — the slowest stage sets the whole pace.
Recall Name the 5 stages in order and one job of each.
IF (fetch instruction at PC), ID (decode + read registers), EX (ALU compute / address calc), MEM (data memory read/write), WB (write result to register file).
Recall Why is max speedup equal to the number of stages?
Because for large n one instruction finishes every cycle (throughput 1/t) vs 1/(kt) non-pipelined, a k× ratio; the k−1 fill cycles become negligible.
Recall Does pipelining reduce latency of a single instruction?
No. Latency stays k cycles (slightly worse with register overhead). It improves throughput.
What are the 5 stages of the classic RISC pipeline (in order)?
IF, ID, EX, MEM, WB
What does the IF stage do?
Fetches the instruction from memory at the current PC.
What does the ID stage do?
Decodes the instruction and reads source operands from the register file.
What does the EX stage do?
Performs the ALU operation or calculates a memory address.
What does the MEM stage do?
Accesses data memory (loads read, stores write).
What does the WB stage do?
Writes the result back into the register file.
Formula for pipelined time of n instructions, k stages, stage time t?
T = (k + n - 1) * t
Formula for ideal pipeline speedup?
S = nk / (k + n - 1), approaching k as n→∞.
What is the maximum theoretical speedup of a k-stage pipeline?
k (the number of stages).
What is the purpose of pipeline registers?
To latch each instruction's intermediate state between stages so it isn't overwritten by the next instruction.
Does pipelining reduce single-instruction latency?
No — only throughput improves; latency stays ~k cycles.
What sets the pipeline clock period?
The slowest stage delay plus pipeline-register overhead.
Why do small n give poor speedup?
The k−1 fill (warm-up) cycles dominate when few instructions are processed.
Socho ek instruction ko complete hone ke liye 5 chote-chote kaam karne padte hain: pehle memory se instruction laana (IF), phir use samajhna aur registers padhna (ID), phir ALU se calculation (EX), phir data memory access (MEM), aur last me result wapas register me likhna (WB). Agar hum ek instruction poora khatam karke hi agla shuru karein, to har waqt sirf ek hi hardware part busy rahega aur baaki khaali baithe rahenge — bahut bekaar.
Pipelining ka jugaad yeh hai: jaise hi instruction 1 IF se nikal kar ID me jaata hai, instruction 2 turant IF me ghus jaata hai. Isse har stage hamesha kaam karta rehta hai, bilkul laundry ya sandwich assembly line ki tarah. Beech me jo "pipeline registers" hote hain wo har instruction ka adha-pakaa kaam hold karke rakhte hain taaki agla instruction usse mita na de.
Yaad rakhna important baat: pipelining se ek single instruction tez nahi hoti — uski latency abhi bhi 5 cycle hi hai. Jo improve hota hai wo throughput hai, yaani per second kitne instructions complete hote hain. Formula: n instructions ke liye time =(k+n−1)t aur speedup =k+n−1nk, jo bade n par stages ki sankhya k ke kareeb pahunch jaata hai (yahan 5x tak).
Par real life me itna perfect 5x nahi milta — kyunki hazards (data/control), unbalanced stages, aur shuruaati fill cycles speedup ko kam kar dete hain. Isliye next topics hazards aur forwarding bhi padhna zaroori hai.
