Pipelining — 5-stage pipeline, each stage — Hinglish notes

4.1.18 · Coding › Computer Architecture (Deep)

WHAT hai ek pipeline?

Classic RISC 5-stage pipeline (MIPS-style) ke stages hain:

#	Stage	Name	Kya karta hai
1	IF	Instruction Fetch	PC par memory se instruction read karo
2	ID	Instruction Decode / register read	Opcode decode karo, source registers read karo
3	EX	Execute / address calc	ALU result ya memory address compute karta hai
4	MEM	Memory access	Load/store data memory ko read ya write karta hai
5	WB	Write Back	Result ko register file mein write karo

Figure — Pipelining — 5-stage pipeline, each stage

Speedup ko SCRATCH SE derive karna

HOW hum $n$ instructions ka time derive karte hain.

Maano har stage $t$ time leti hai. Ek akeli non-pipelined instruction ko saari $k$ stages chahiye: $T_{instr} = k \cdot t$

Non-pipelined, $n$ instructions ek ke baad ek run hoti hain: $T_{seq} = n \cdot k \cdot t$

Pipelined: clock period slowest stage mein fit hona chahiye, to cycle time $= t$ (balanced stages assume karte hue). Pehli instruction ko pipe fill karne mein $k$ cycles lagte hain. Uske baad, har cycle mein ek instruction finish hoti hai. To instructions $2, 3, \dots, n$ ek-ek cycle add karte hain: $T_{pipe} = fill k \cdot t + remaining (n - 1) \cdot t = (k + n - 1) t$

Throughput vs Latency

Clock faster kyun run kar sakta hai

Reality mein stages unbalanced hote hain aur registers latency $t_{reg}$ add karte hain: $t_{clk} = max (stage delays) + t_{reg}$ Isliye hum stages balance karne ki koshish karte hain — slowest stage poori pace set karta hai.

Common mistakes (Steel-manned)

Active Recall

Recall 5 stages ko order mein naam bolo aur har ek ka ek kaam batao.

IF (PC par instruction fetch karo), ID (decode + registers read karo), EX (ALU compute / address calc), MEM (data memory read/write), WB (result ko register file mein likho).

Recall Max speedup stages ki sankhya ke barabar kyun hoti hai?

Kyunki bade $n$ ke liye har cycle mein ek instruction finish hoti hai (throughput $1/ t$ ) vs non-pipelined $1/ (k t)$ , jo $k \times$ ratio hai; $k - 1$ fill cycles negligible ho jaate hain.

Recall Kya pipelining ek single instruction ki latency reduce karta hai?

Nahi. Latency $k$ cycles par rehti hai (register overhead ke saath thodi aur buri). Yeh throughput improve karta hai.

Classic RISC pipeline ke 5 stages (order mein) kya hain?

IF, ID, EX, MEM, WB

IF stage kya karta hai?

Current PC par memory se instruction fetch karta hai.

ID stage kya karta hai?

Instruction decode karta hai aur register file se source operands read karta hai.

EX stage kya karta hai?

ALU operation perform karta hai ya memory address calculate karta hai.

MEM stage kya karta hai?

Data memory access karta hai (loads read karte hain, stores write karte hain).

WB stage kya karta hai?

Result ko register file mein wapas write karta hai.

n instructions, k stages, stage time t ke liye pipelined time ka formula?

T = (k + n - 1) * t

Ideal pipeline speedup ka formula?

S = nk / (k + n - 1), n→∞ par k approach karta hai.

k-stage pipeline ka maximum theoretical speedup kya hai?

k (stages ki sankhya).

Pipeline registers ka purpose kya hai?

Har instruction ki intermediate state ko stages ke beech latch karna taaki agle instruction se overwrite na ho.

Kya pipelining single-instruction latency reduce karta hai?

Nahi — sirf throughput improve hota hai; latency ~k cycles par rehti hai.

Pipeline clock period kya set karta hai?

Slowest stage delay plus pipeline-register overhead.

Chhota n poor speedup kyun deta hai?

Jab thodi instructions process hoti hain, k−1 fill (warm-up) cycles dominate karte hain.

Connections

Pipeline Hazards (Data, Control, Structural)
Forwarding and Bypassing
Branch Prediction
Single-cycle vs Multi-cycle Datapath
Clock Frequency and CPI
Amdahl's Law
Superscalar and Out-of-Order Execution