Fetch-decode-execute cycle — step by step

WHAT is it?

WHY does this even need to exist? Because a program is just a list of instructions sitting in memory. The CPU has no magic — it needs a mechanical procedure to (a) know which instruction is next, (b) bring it close enough to act on, and (c) understand it before acting. The cycle is that procedure.

The key parts (so the steps make sense)

PC — Program Counter: holds the address of the next instruction. WHY: the CPU must remember its place in the list, like a finger on a recipe line.
MAR — Memory Address Register: holds the address we want to read from / write to.
MDR — Memory Data Register: holds the data/instruction just fetched from memory.
CIR — Current Instruction Register: holds the instruction currently being decoded/executed.
ALU — Arithmetic Logic Unit: does maths (+ − ×) and logic (AND, compare).
CU — Control Unit: the boss that decodes and sends signals.

Figure — Fetch-decode-execute cycle — step by step

HOW it works — derived step by step

Let's build the cycle from scratch, asking at each move: "what does the CPU not yet know, and what does it need?"

Step 1 — FETCH

Why each line?

MAR ← PC — Why? Memory only responds to an address, and addresses must travel on the address bus from the MAR. So we copy "where next" into the MAR.
MDR ← [MAR] — Why? The instruction physically lives in RAM. We send the address out, RAM replies on the data bus, and the reply lands in the MDR.
CIR ← MDR — Why? The MDR is a temporary "loading dock"; the instruction we'll work on must sit in the CIR so the next fetch doesn't overwrite it.
PC ← PC + 1 — Why now? We increment early, before execution, so the PC already points to the next instruction. (If a jump happens during execute, it simply overwrites the PC.)

Step 2 — DECODE

The control unit splits the instruction in the CIR into two parts: $\underbrace{\texttt{1001}}_{\text{opcode}}\;\underbrace{\texttt{0110}}_{\text{operand}}$

Opcode = what to do (e.g. ADD, LOAD, STORE, JUMP).
Operand = what to do it to (an address, a register, or a value).

Why split it? The CPU must turn one binary blob into concrete control signals — "open this gate, route that bus." It cannot act until it knows the opcode.

Step 3 — EXECUTE

The CU fires the control signals; the ALU and registers do the work. Examples:

ADD → ALU adds operand to the accumulator.
STORE → put a value into memory.
JUMP n → overwrite PC ← n (this is how loops/ifs work!).

Then: back to Fetch. Forever (until halt).

Worked examples

Common mistakes (steel-manned)

Recall Feynman: explain to a 12-year-old

Imagine you're following a recipe, but you can only see one line at a time. Your finger points to the line (that's the PC). You read the line (fetch), you understand what it's telling you to do — "add 2 eggs" (decode), and then you actually do it (execute). Then your finger slides to the next line and you do it all again. A computer does this billions of times a second — it's just a super fast cook who can only read one tiny line at a time but never gets tired!

Active recall

What are the three stages of the instruction cycle, in order?

Fetch, Decode, Execute.

Which register holds the address of the next instruction?

The Program Counter (PC).

In fetch, why is the PC incremented before execute runs?

So a jump in execute can overwrite the PC cleanly, leaving the right address for the next fetch.

Which register temporarily holds data/instruction just read from RAM?

The Memory Data Register (MDR).

Which register holds the instruction currently being decoded?

The Current Instruction Register (CIR).

What two parts does the control unit split an instruction into during decode?

The opcode (what to do) and the operand (what to do it to / address).

What does the ALU stand for and do?

Arithmetic Logic Unit — performs arithmetic and logic operations.

How does a JUMP instruction create a loop?

It overwrites the PC with a target address, so the next fetch goes back to that address instead of moving forward.

Roughly how many cycles per second does a 3 GHz CPU run?

About 3×10⁹ (3 billion).

Which bus carries the address from the MAR to memory?

The address bus (data returns on the data bus).

Connections

CPU architecture (Von Neumann) — why instructions and data share one memory.
Registers and the ALU — the storage the cycle relies on.
Buses — address, data, control — the wires the micro-steps use.
Clock speed and performance — how cycle rate maps to GHz.
Machine code and opcodes — what gets decoded.
Pipelining — overlapping cycles to go faster.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, CPU ek bahut tez lekin bahut "buddhu" worker hai — wo ek baar mein sirf ek chhoti si instruction kar sakta hai. Program toh bas instructions ki ek list hai jo RAM mein padi hai. CPU ko ek fixed tareeka chahiye us list ko chalane ka — wahi hai fetch–decode–execute cycle. Pehle fetch: next instruction ko memory se utha kar CPU ke andar laao. Phir decode: control unit samajhta hai ki instruction ka matlab kya hai (kaunsa kaam, kis cheez pe). Phir execute: ALU ya control unit asli kaam kar deta hai. Iske baad loop wapas shuru — yahi cheez computer din-raat karta rehta hai.

Isme PC (Program Counter) sabse important hai — wo yaad rakhta hai ki agli instruction kahaan hai, jaise recipe pe ungli rakhi ho. Fetch ke time hi PC ko +1 kar dete hain, taaki agli line ready rahe. Important trick: JUMP instruction execute ke time PC ko overwrite kar deta hai — isi se loops aur if-else bante hain. MAR address bhejta hai, MDR data wapas laata hai, CIR instruction ko hold karke rakhta hai jab tak decode/execute na ho jaaye.

Yeh topic 80/20 wala hai: agar tum yeh teen steps aur PC ka role samajh gaye, toh tumhe computer ki poori working ka core mil gaya. Aur jab koi bole "3 GHz CPU", toh matlab ye cycle lagbhag 3 billion baar per second chalti hai. Exam mein bas micro-steps ka order aur "PC pehle increment hota hai" yaad rakhna — yeh log galat karte hain. Practice ke liye ek ADD aur ek JUMP instruction khud trace kar lo, dimaag mein cycle clear ho jaayega.

Test yourself — How Computers Work

Connections