Intuition The 30-second picturex86 is a CISC (Complex Instruction Set Computer) family that started in 1978 with Intel's 8086 and grew by never throwing anything away . Every generation added features but kept old ones working, so a modern CPU can still run 1980s DOS code. The result is a huge, irregular, backward-compatible instruction set that dominates desktops, laptops, and servers.
Intuition The core reason:backward compatibility above all else
When the 8086 shipped, memory and disk were tiny and expensive . A CISC philosophy — pack a lot of work into each instruction — made programs smaller (fewer bytes to store) and let programmers hand-write dense assembly. Later, Intel could not break the millions of existing programs, so each new chip extended the old one instead of redesigning it. Every quirk you'll meet (variable-length instructions, segmentation, few registers) is a fossil of this history.
WHAT this gives us / costs us:
✅ A single binary runs on 40 years of hardware.
❌ Instructions are variable length (1–15 bytes), making decoding hard.
❌ The register set is small and irregular compared to RISC.
A family of CISC instruction set architectures (ISAs), backward-compatible with the Intel 8086. Key members: 8086 (16-bit) → 80386 (32-bit, "IA-32") → AMD64/x86-64 (64-bit, the modern norm).
Definition Register (in x86)A small, named on-CPU storage cell the ALU reads/writes directly — the fastest memory in the machine. x86-64 has 16 general-purpose 64-bit registers.
The general-purpose registers grew by extension , which is why their names look layered:
64-bit
32-bit
16-bit
8-bit (low)
traditional role
RAX
EAX
AX
AL
Accumulator
RBX
EBX
BX
BL
Base
RCX
ECX
CX
CL
Counter (loops)
RDX
EDX
DX
DL
Data
RSP
ESP
SP
—
Stack Pointer
RBP
EBP
BP
—
Base/Frame Pointer
RSI
ESI
SI
—
Source Index
RDI
EDI
DI
—
Dest Index
R8–R15
R8D…
R8W…
R8B…
added in x86-64
Intuition Why one register has 4 namesAL (8 bits) sits inside AX (16) which sits inside EAX (32) which sits inside RAX (64). Writing AL only touches the low byte. This nesting is literally the 8086 register grown outward, generation by generation — a fossil record you can address at any layer.
Intuition The execution cycleSame as any CPU: fetch → decode → execute → write-back . What makes x86 special is the decode step, because instructions have no fixed length.
An x86 instruction is a sequence of fields, each optional except the opcode:
[Prefixes] → [Opcode] → [ModR/M] → [SIB] → [Displacement] → [Immediate] \text{[Prefixes]} \;\to\; \text{[Opcode]} \;\to\; \text{[ModR/M]} \;\to\; \text{[SIB]} \;\to\; \text{[Displacement]} \;\to\; \text{[Immediate]} [Prefixes] → [Opcode] → [ModR/M] → [SIB] → [Displacement] → [Immediate]
Prefix : modifiers (operand size, REX for 64-bit/extra registers, lock, repeat).Opcode : what to do (ADD, MOV…).ModR/M + SIB : encode which registers/memory operands and the addressing mode.Displacement / Immediate : constants baked into the instruction.
Intuition Why segmentation existedThe 8086 had 16-bit registers but Intel wanted a 20-bit address space (1 MB). You cannot point to a 20-bit address with a 16-bit register. Fix: combine two 16-bit numbers.
Worked example 1 — Compute a real-mode physical addressSegment = 0x1000, Offset = 0x0020. Find the physical address.
( 0 x 1000 × 16 ) + 0 x 0020 = 0 x 10000 + 0 x 20 = 0 x 10020 (\,0x1000 \times 16\,) + 0x0020 = 0x10000 + 0x20 = \mathbf{0x10020} ( 0 x 1000 × 16 ) + 0 x 0020 = 0 x 10000 + 0 x 20 = 0x10020 Why this step? × 16 \times 16 × 16 within the segment.
Worked example 3 — Why a MOV can be 2 or 7 bytesmov al, bl encodes in ~2 bytes (opcode + ModR/M). mov rax, 0x1122334455667788 needs a REX prefix + opcode + an 8-byte immediate ≈ 10 bytes.
Why this step? The immediate constant lives inside the instruction, so bigger constants literally make the instruction longer — the direct cause of variable length.
Common mistake "x86 is 64-bit because RAX is 64 bits — so it was always 64-bit."Why it feels right: modern machines are all 64-bit, and the registers are 64 bits wide, so it seems intrinsic.
The fix: x86 began 16-bit (8086), became 32-bit (80386, "IA-32"), and only reached 64 bits with AMD64 in 2003 — designed by AMD , not Intel. RAX is EAX extended.
Common mistake "x86 is CISC, so it's slow / RISC won."Why it feels right: RISC's clean fixed-length design is easier to pipeline.
The fix: Modern x86 CPUs internally translate CISC instructions into RISC-like micro-ops (µops) and execute those out-of-order. So x86 is CISC on the outside, RISC-ish on the inside — the ISA and the microarchitecture are different things.
Common mistake "Segment × 16 means multiply is happening at runtime — expensive!"Why it feels right: "×16" reads like arithmetic.
The fix: ×16 is a shift left by 4 bits , done by wiring, essentially free in hardware.
Recall Explain to a 12-year-oldImagine a toy robot from 1978. Every year the company sold a better robot, but they promised: "all your old cassettes will still play." So they never removed old buttons, they only added new ones. Today's robot has 40 years of buttons stacked up — powerful, but a bit of a messy control panel. That's x86: super compatible, a little cluttered, and still going strong.
Mnemonic Remember the register roles"A B C D — Accumulate, Base, Count, Data." And for the extras: SI/DI = Source In / Dest In (data flows from SI to DI in string copies). "REX gives you eXtra registers (R8–R15) and 64-bit width."
Why does an x86 instruction have variable length, and why is that costly?
Derive the real-mode physical address of segment 0x0400, offset 0x0010.
Who designed the 64-bit extension, and what is RAX to EAX?
What does a modern x86 CPU do internally with a CISC instruction?
x86 belongs to which ISA design philosophy? CISC (Complex Instruction Set Computer)
What is the defining design constraint of the whole x86 family? Backward compatibility with the Intel 8086
How long can an x86 instruction be? Variable length, 1 to 15 bytes
Formula for a real-mode physical address? (Segment × 16) + Offset = (Segment << 4) + Offset
Why multiply the segment by 16? To shift the 16-bit segment left by 4 bits, spanning a 20-bit (1 MB) address with a 16-bit offset
What is EAX relative to RAX? EAX is the low 32 bits of the 64-bit RAX register
What is AL relative to AX? AL is the low 8 bits of the 16-bit AX register
Who introduced 64-bit x86 and what is it called? AMD, in 2003; called AMD64 / x86-64
Name the 8 legacy general-purpose 64-bit registers. RAX, RBX, RCX, RDX, RSP, RBP, RSI, RDI
What does the REX prefix enable? 64-bit operand size and access to extra registers R8–R15
What does a modern x86 CPU do with a CISC instruction internally? Decodes it into RISC-like micro-ops (µops) executed out-of-order
Why is variable-length encoding costly? You can't locate instruction n+1 until you've fully decoded instruction n, complicating the decoder
The four fetch–execute stages? Fetch, Decode, Execute, Write-back
In long (64-bit) mode, what happened to segmentation? Mostly disabled — a flat memory model is used, though segment registers still exist
Tiny expensive memory 1978
Variable length instructions
Small irregular register set
Nested register names RAX EAX AX AL
Fetch decode execute writeback
Intuition Hinglish mein samjhoDekho, x86 ka pura funda ek line mein: backward compatibility . 1978 mein Intel ka 8086 aaya, aur uske baad har naya chip purane ko todta nahi, balki usme feature add karta gaya. Isiliye aaj ka modern 64-bit CPU bhi 40 saal purana DOS program chala sakta hai. Yahi wajah hai ki x86 ek CISC architecture hai — matlab ek instruction bahut saara kaam karta hai, aur instructions ki length fixed nahi, 1 se 15 bytes tak variable hoti hai.
Registers ki nesting samajhna zaroori hai. RAX (64-bit) ke andar EAX (32-bit), uske andar AX (16-bit), aur uske andar AL (8-bit). Yeh ek hi physical register hai jise alag-alag naam se, alag-alag layer tak, access kar sakte ho. Yeh koi copy nahi hoti — bas low bits ka window hai. Isi tarah yeh sab historically evolve hua: 16-bit se 32-bit (80386, IA-32) se 64-bit (AMD64, jo 2003 mein AMD ne banaya, Intel ne nahi).
Ek important cheez: purane 8086 mein memory access ke liye segmentation thi, kyunki 16-bit register se 20-bit (1 MB) address point karna possible nahi tha. Formula tha: Physical Address = Segment × 16 + Offset . Yahan ×16 ka matlab hai left shift by 4 bits — hardware mein yeh basically free hai, koi mehenga multiply nahi.
Aur ek myth tod do: "CISC slow hai, RISC jeet gaya" — galat. Modern x86 chip andar-andar CISC instruction ko chhote micro-ops (µops) mein todta hai aur unhe RISC ki tarah out-of-order chalata hai. Toh x86 bahar se CISC, andar se RISC-jaisa hai. Exam mein yeh distinction — ISA vs microarchitecture — bahut kaam aata hai.
