Noesis
5.1.4Instruction Set Architecture (ISA)

Register file organization

2,128 words10 min readdifficulty · medium6 backlinks
🇮🇳 Yeh note Hinglish mein padho →

WHAT is a register file?

Key parameters that fully describe a register file:

Symbol Meaning Typical value
N=2kN = 2^k number of registers 32 (so k=5k=5)
nn width of each register (bits) 32 or 64
RR number of read ports 2
WW number of write ports 1

HOW is it built? (from first principles)

We build up from a single storage bit and derive why the port structure looks the way it does.

Step 1 — one storage cell

Each bit is a D flip-flop / latch that holds its value across clock edges. A register is nn such cells sharing one write-enable line.

Step 2 — selecting which register to read

We have N=2kN=2^k registers but only want one on the read bus. That's exactly a multiplexer: a 2k2^k-to-1 MUX selects the addressed register onto a read port.

Why this step? Reading is "pick one of many onto a wire" → that's the definition of a MUX.

Step 3 — selecting which register to write

Writing is the reverse: one incoming data value must land in exactly one register. We use a ==kk-to-2k2^k decoder== whose outputs are ANDed with a global WriteEnable. Only the decoded line's register captures data on the clock edge.

Why this step? Writing is "route one wire to one of many" → that's a decoder + enable.

Step 4 — multiple ports = replicate the read MUX

Each independent read port needs its own MUX so two registers can be read at once. Two read ports ⇒ two 2k2^k-to-1 MUXes reading the same flip-flop outputs.

Figure — Register file organization

Special register: R0 hardwired to zero

Worked Examples

Common Mistakes (Steel-manned)

Active Recall

Recall Test yourself (answers hidden)
  1. How many address bits for 64 registers? → log⁡264=6\log_2 64 = 6.
  2. Why 2 read ports + 1 write port? → matches a 2-operand ALU op rd = rs1 op rs2.
  3. Read is built from a ___ , write from a ___ ? → MUX ; decoder+enable.
  4. How does area scale with ports? → (R+W)2(R+W)^2.
  5. What does R0 hardwired to 0 buy you? → free mov, nop, constant source; saves opcodes.
Recall Feynman: explain to a 12-year-old

Imagine you're doing math homework. The warehouse is your bookshelf across the room (slow to reach) — that's memory. The register file is the few pencils and scraps of paper on your desk. To add two numbers you need to see both at once (two eyes = two read ports) and have one hand to write the answer (one write port). If you wanted to solve two problems at the same time you'd need four eyes and two hands — much more crowded desk! That crowding growing super fast is why we don't give ourselves a hundred hands.

Connections

  • Instruction Set Architecture (ISA) — the register file is the ISA's visible state.
  • Memory Hierarchy — registers are the fastest, smallest tier above cache.
  • Datapath and ALU — read ports feed the ALU, write port stores the result.
  • Pipeline Hazards — read-during-write and forwarding logic.
  • Multiplexers and Decoders — the building blocks of read/write selection.
  • RISC vs CISC — RISC's load/store design leans hard on many registers.
How many address bits are needed to select one of NN registers?
⌈log⁡2N⌉\lceil \log_2 N \rceil bits.
In a register file, what hardware performs a read (select one of many onto a bus)?
A 2k2^k-to-1 multiplexer, one per read port.
In a register file, what hardware performs a write (route data to one register)?
A kk-to-2k2^k decoder ANDed with a global write-enable.
Why do typical CPUs use 2 read ports and 1 write port?
A 2-operand instruction rd = rs1 op rs2 needs two simultaneous operand reads and one result write.
How does register-file area scale with the number of ports?
Roughly A∝N n (R+W)2A \propto N\,n\,(R+W)^2 — the port count enters as a square.
Why is register 0 often hardwired to zero?
It provides a free constant 0, letting mov/nop/clear be synthesized from add, saving opcode space.
Total state bits in a register file of NN registers each nn bits wide?
N×nN \times n bits (independent of port count).
If issue width doubles (all ops need 2R+1W), how much bigger is the file?
Ports go 2→42{\to}4 read, 1→21{\to}2 write; area factor =(6/3)2=4×=(6/3)^2 = 4\times.
What is the read-during-write hazard?
Reading a register in the same cycle it's being written; result depends on read-first vs write-first design; solved by bypass/forwarding.

Concept Map

holds

selected by

built from

n cells share

read via

write via

one per

routes to

serve

serve

needs 2 reads 1 write

drives cost

drives cost

Register File

2^k registers of n bits

k-bit address

D flip-flop cells

Write-enable line

2^k-to-1 MUX

k-to-2^k decoder + enable

Read ports R=2

Write ports W=1

2-operand ALU

add rd rs1 rs2

Area proportional to N n R+W squared

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, register file basically CPU ke andar ki chhoti si high-speed memory hai — jaise aapke desk pe rakhe do-teen pencils. Main memory to door ki warehouse hai (slow), par registers haath mein hote hain, isliye ek hi clock cycle mein data mil jaata hai. Agar NN registers hain to unme se ek ko choose karne ke liye log⁡2N\log_2 N bits ki address chahiye — 32 registers matlab 5 bits.

Ab construction samjho: read ka matlab hai "many me se ek ko wire pe laao" — yeh kaam MUX karta hai. Write ka matlab "ek data ko ek specific register me daalo" — yeh decoder + write-enable karta hai. ALU ka typical kaam hota hai add rd, rs1, rs2, isliye ek saath do read (rs1, rs2) aur ek write (rd) chahiye — isliye 2 read port + 1 write port standard hai.

Sabse important trick: ports mehnge hote hain! Area roughly N⋅n⋅(R+W)2N \cdot n \cdot (R+W)^2 ke hisaab se badhta hai — matlab ports double karo to cost square ho jaati hai, isliye superscalar CPUs bahut costly ho jaate hain. Aur ek chhoti si smart baat: R0 ko hardwire karke 0 rakh dete hain — isse mov, nop, clear jaise operations free me add se ban jaate hain, opcode bachta hai. Yaad rakhna mnemonic: "Do aankhein, ek haath — aur cost lagta hai SQUARE."

Go deeper — visual, from zero

D1FoundationsEvery symbol from zero · 1,963 wordsD2Visual walkthroughThe derivation in pictures · 2,435 wordsD3Worked examplesEvery scenario covered · 2,654 wordsD4ExercisesGraded, full solutions · 2,454 wordsD5Question bankConcept traps, quick reveals · 1,493 words

Test yourself — Instruction Set Architecture (ISA)

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Connections

ISA (Instruction Set Architecture) — RISC vs CISCCoding · 4.1.3Memory hierarchy — registers, cache (L1 - L2 - L3), RAM, SSD, HDD — speed - size trade-offsCoding · 1.1.9Pipeline hazards — structural, data (RAW - WAR - WAW), controlCoding · 4.1.19CISC vs RISC philosophiesHardware · 5.1.1ISA (Instruction Set Architecture) — RISC vs CISCCoding · 4.1.3ARM architecture intro — used in embedded - aerospaceCoding · 4.1.4Memory addressing modes — immediate, register, direct, indirect, indexedCoding · 4.1.8Instruction formats and encodingHardware · 5.1.2Addressing modesHardware · 5.1.3x86 architecture overviewHardware · 5.1.5