Register file organization — Hinglish notes

5.1.4 · Hardware › Instruction Set Architecture (ISA)

Register file KIYA hai?

Key parameters jo ek register file ko poora describe karte hain:

Symbol	Meaning	Typical value
$N = 2^{k}$	registers ki sankhya	32 (to $k = 5$ )
$n$	har register ki width (bits)	32 ya 64
$R$	read ports ki sankhya	2
$W$	write ports ki sankhya	1

Yeh KAISE banta hai? (first principles se)

Hum ek single storage bit se shuru karte hain aur derive karte hain ki port structure aisa kyun dikhta hai.

Step 1 — ek storage cell

Har bit ek D flip-flop / latch hai jo apni value clock edges ke across hold karta hai. Ek register $n$ aise cells hain jo ek write-enable line share karte hain.

Step 2 — kaunsa register read karna hai yeh select karna

Hamare paas $N = 2^{k}$ registers hain lekin read bus par sirf ek chahiye. Yeh bilkul ek multiplexer hai: ek $2^{k}$ -to-1 MUX addressed register ko read port par select karta hai.

Yeh step kyun? Reading matlab "bahut mein se ek ko ek wire par pick karna" → yeh MUX ki definition hai.

Step 3 — kaunse register mein write karna hai yeh select karna

Writing iska ulta hai: ek incoming data value exactly ek register mein jaani chahiye. Hum ek == $k$ -to- $2^{k}$ decoder== use karte hain jinke outputs ek global WriteEnable ke saath AND hote hain. Sirf decoded line ka register clock edge par data capture karta hai.

Yeh step kyun? Writing matlab "ek wire ko bahut mein se ek par route karna" → yeh decoder + enable hai.

Step 4 — multiple ports = read MUX ko replicate karo

Har independent read port ko apna MUX chahiye taaki do registers ek saath read ho sakein. Do read ports ⇒ do $2^{k}$ -to-1 MUXes jo same flip-flop outputs read karte hain.

Special register: R0 hardwired to zero

Worked Examples

Common Mistakes (Steel-manned)

Active Recall

Recall Khud test karo (answers hidden)

64 registers ke liye kitne address bits? → $lo g_{2} 64 = 6$ .
2 read ports + 1 write port kyun? → ek 2-operand ALU op rd = rs1 op rs2 se match karta hai.
Read ek ___ se banta hai, write ek ___ se? → MUX ; decoder+enable.
Area ports ke saath kaise scale karta hai? → $(R + W)^{2}$ .
R0 hardwired to 0 se kya milta hai? → free mov, nop, constant source; opcodes bachte hain.

Recall Feynman: ek 12-saal ke bachhe ko samjhao

Socho tum math homework kar rahe ho. Warehouse woh bookshelf hai kamre ke doosri taraf (pahunchna slow hai) — yeh memory hai. Register file woh kuch pencils aur kagaz hain jo tumhari desk par hain. Do numbers add karne ke liye tumhe dono ek saath dekhne hain (do aankhein = do read ports) aur ek haath chahiye answer likhne ke liye (ek write port). Agar tum ek saath do problems solve karna chahte to tumhe chaar aankhein aur do haath chahiye hote — bahut zyada crowded desk! Woh crowding bahut tezi se badhna hi reason hai ki hum khud ko sau haath nahi dete.

Connections

Instruction Set Architecture (ISA) — register file ISA ki visible state hai.
Memory Hierarchy — registers cache ke upar sabse fast, sabse choti tier hain.
Datapath and ALU — read ports ALU ko feed karte hain, write port result store karta hai.
Pipeline Hazards — read-during-write aur forwarding logic.
Multiplexers and Decoders — read/write selection ke building blocks.
RISC vs CISC — RISC ka load/store design bahut saare registers par heavily depend karta hai.

N

registers mein se ek select karne ke liye kitne address bits chahiye?

⌈ lo g_{2} N ⌉

bits.

2^{k}

-to-1 multiplexer, har read port ke liye ek.

k

-to-

2^{k}

decoder jo global write-enable ke saath AND hota hai.

Typical CPUs 2 read ports aur 1 write port kyun use karte hain?

Ek 2-operand instruction rd = rs1 op rs2 ko do simultaneous operand reads aur ek result write chahiye.

Roughly

A \propto N n (R + W)^{2}

— port count square mein aata hai.

Yeh ek free constant 0 provide karta hai, jisse mov/nop/clear ko add se synthesize kiya ja sake, opcode space bachta hai.

N

registers mein se har ek

n

bits wide register file mein total state bits?

N \times n

bits (port count se independent).

Agar issue width double ho (sab ops ko 2R+1W chahiye), to file kitni badi hogi?

Ports

2 \to 4

read,

1 \to 2

write ho jaate hain; area factor

= (6/3)^{2} = 4 \times

Read-during-write hazard kya hai?

Ek register ko usi cycle mein read karna jisme woh write ho raha hai; result read-first vs write-first design par depend karta hai; bypass/forwarding se solve hota hai.