Register file organization: Worked examples — Hardware deep dive

Before anything else, let us re-earn the four symbols we will use over and over, in plain words:

The single cost fact we lean on everywhere:

The scenario matrix

Every register-file numeric question falls into one of these boxes. The job of this page is to hit every row.

#	Case class	What makes it tricky	Example that hits it
A	$N$ is an exact power of 2	clean $lo g_{2}$	Ex 1
B	$N$ is not a power of 2	must round up (ceiling)	Ex 2
C	Degenerate: $N = 1$	$lo g_{2} 1 = 0$ address bits	Ex 3
D	Total stored state	$N \cdot n$ , ports don't count	Ex 4
E	Superscalar port scaling	$(R + W)^{2}$ area ratio	Ex 5
F	Limiting case: many ports	how fast cost blows up	Ex 6
G	Read-during-write timing	old vs new value, no arithmetic trap	Ex 7
H	Real-world word problem	translate English → $N, k, R, W$	Ex 8
I	Exam twist: instruction encoding budget	mixing $k$ with opcode bits	Ex 9
J	R0 degenerate storage	one register stores nothing	Ex 10

Prerequisite building blocks live in Multiplexers and Decoders and Datapath and ALU; the timing row leans on Pipeline Hazards.

Worked Examples

Cell B — not a power of two (the ceiling trap)

Cell C — the degenerate single register

Cell D — total stored state (ports don't count)

Cell E — superscalar port scaling

Worked example Example 5 — going from 1-wide to 2-wide issue

Baseline file: $R = 2, W = 1$ . A 2-issue superscalar core needs to run two adds per cycle, each doing 2 reads + 1 write. By what factor does the area law grow?

Forecast: double the work — double the area? Guess.

New read ports: $2 ops \times 2 reads = 4$ , so $R = 4$ . New write ports: $2 \times 1 = 2$ , so $W = 2$ . Why this step? Ports = simultaneous accesses; two independent 2-read/1-write ops need all their operands live at once.
Area ratio $= \frac{( R _{new} + W _{new} ) ^{2}}{( R _{old} + W _{old} ) ^{2}} = \frac{( 4 + 2 ) ^{2}}{( 2 + 1 ) ^{2}}$ . Why this step? The area law $A \propto (R + W)^{2}$ means only the total port count matters; take the ratio to cancel $N \cdot n$ .
$= \frac{36}{9} = 4$ .

Verify: $(4 + 2)^{2} = 36$ , $(2 + 1)^{2} = 9$ , $36/9 = 4$ . ✓ Doubling issue width quadrupled the register-file area — the reason wide cores split the file into banks (see RISC vs CISC and Pipeline Hazards).

Cell F — the limiting case (how fast does it blow up?)

Cell G — read-during-write timing

Worked example Example 7 — reading R5 in the same cycle it's written

In one clock cycle, read port 1 addresses R5 while the write port stores a new value into R5. What comes out on the read port?

Forecast: old value, new value, or "it depends"?

There is no arithmetic here — it's a timing policy question. List the two policies:
- Read-first: the read MUX samples the old flip-flop value before the clock edge captures the new one ⇒ old value.
- Write-first (internal forwarding): the file bypasses the incoming write data straight to the read port ⇒ new value. Why this step? Both read and write happen "in the same cycle", so the order within the cycle is a design choice, not a fixed truth.
Real pipelines add a forwarding/bypass MUX so a dependent instruction one cycle later still sees fresh data. Why this step? Without it, the reader gets stale data — a read-after-write data hazard (Pipeline Hazards).

Verify (sanity): the state stored is unambiguous — after the edge, R5 holds the new value regardless of policy. Only what appeared on the read wire that cycle differs. ✓ No number to compute; the answer is "policy-dependent, and forwarding fixes the hazard."

Cell H — real-world word problem

Cell I — exam twist: instruction encoding budget

Worked example Example 9 — do three register fields fit?

An ISA uses a fixed 32-bit instruction word. With $N = 32$ registers, a 3-operand instruction add rd, rs1, rs2 must encode three register names. How many bits are left for the opcode?

Forecast: guess how many bits the three register fields eat, then subtract.

Each register field is $k = lo g_{2} 32 = 5$ bits (Ex 1). Three fields: $3 \times 5 = 15$ bits. Why this step? Every named operand needs its own $k$ -bit selector — the address width from the left-hand law.
Opcode bits left $= 32 - 15 = 17$ bits. Why this step? The instruction word is a fixed budget; register fields and opcode share it.
Twist check: if the designer bumped to $N = 64$ ( $k = 6$ ), three fields cost $3 \times 6 = 18$ bits, leaving $32 - 18 = 14$ for opcode. Why this step? This is the real cost of "more registers is always better" (see the parent's mistake box) — every extra address bit is stolen from opcode space, in every instruction.

Verify: $3 \times 5 = 15$ , $32 - 15 = 17$ ✓; and $3 \times 6 = 18$ , $32 - 18 = 14$ ✓. More registers ⇒ fewer opcodes. Trade-off confirmed.

Cell J — R0 degenerate storage

Worked example Example 10 — how many flip-flops does R0 use?

RISC-V's R0 is hardwired to 0: it always reads as 0 and ignores writes. In a 32-register, 32-bit file, how many actual storage flip-flops exist, and what does R0 cost?

Forecast: is it $32 \times 32$ flip-flops, or fewer?

Naively, state $= N \cdot n = 32 \times 32 = 1024$ bits. Why this step? The Cell-D formula assumes every register stores real bits.
But R0 stores nothing — its read line is tied to logic 0, no flip-flops built. So real flip-flops $= (32 - 1) \times 32 = 31 \times 32 = 992$ . Why this step? A hardwired constant needs no memory cell; only the address slot is reserved.
R0's hardware cost: essentially zero flip-flops, yet it buys free mov, nop, and a constant-0 source.

Verify: $32 \times 32 = 1024$ ; $31 \times 32 = 992$ ; saved $= 1024 - 992 = 32$ flip-flops. ✓ One register's worth of storage saved and you gain synthetic instructions — the best kind of degenerate case.

Active Recall

Recall Which matrix cell is each trap?

40 registers → address bits? ::: Cell B (ceiling): $⌈ lo g_{2} 40 ⌉ = 6$ .
Does a 3rd read port change total stored bits? ::: No — Cell D: state is $N \cdot n$ only.
4-issue vs 1-issue area factor? ::: Cell F: $16 \times$ , from $(12/3)^{2}$ .
Same-cycle read of a register being written? ::: Cell G: policy-dependent; forwarding gives new value.
Why does 64 registers hurt opcode space? ::: Cell I: $k$ rises to 6, three fields cost 18 bits, leaving fewer opcode bits.

Connections

Register file organization — the parent; this page is its worked-examples drill.
Multiplexers and Decoders — the read MUX / write decoder behind every $k$ here.
Datapath and ALU — why $R = 2, W = 1$ is the natural port shape.
Pipeline Hazards — Cell G's read-during-write and forwarding.
RISC vs CISC — Cell E/F splitting and Cell I's encoding budget.
Memory Hierarchy — why we bother keeping this state on-chip at all.
5.1.04 Register file organization (Hinglish) — same material in Hinglish.

Address bits to select 1 of 40 registers?

⌈ lo g_{2} 40 ⌉ = 6

bits.

Do read/write ports change the total stored bits of a register file?

No; stored bits

= N \cdot n

only. Ports affect area and speed.

Area factor going from a 1-issue (

R = 2, W = 1

) to a 4-issue (

R = 8, W = 4

) file?

(12/3)^{2} = 16 \times

larger.

How many storage flip-flops in a 32×32-bit RISC-V file, given R0 is hardwired?

31 \times 32 = 992

(R0 stores nothing).

Opcode bits left in a 32-bit word after three 5-bit register fields?

32 - 15 = 17