Register file organization: Worked examples — Hinglish deep dive

5.1.4 · D3 · Hardware › Instruction Set Architecture (ISA) › Register file organization

Shuru karne se pehle, un chaar symbols ko plain words mein dobara samajh lete hain jo baar baar use honge:

Ek cost fact jis par hum har jagah rely karte hain:

Scenario matrix

Har register-file numeric question inhi boxes mein se kisi ek mein aati hai. Is page ka kaam hai har row ko cover karna.

#	Case class	Kya tricky banata hai	Example jo isko hit karta hai
A	$N$ exact power of 2 hai	clean $lo g_{2}$	Ex 1
B	$N$ power of 2 nahi hai	upar round karna padta hai (ceiling)	Ex 2
C	Degenerate: $N = 1$	$lo g_{2} 1 = 0$ address bits	Ex 3
D	Total stored state	$N \cdot n$ , ports count nahi hote	Ex 4
E	Superscalar port scaling	$(R + W)^{2}$ area ratio	Ex 5
F	Limiting case: bahut saare ports	cost kitni tezi se badhti hai	Ex 6
G	Read-during-write timing	old vs new value, koi arithmetic trap nahi	Ex 7
H	Real-world word problem	English ko $N, k, R, W$ mein translate karo	Ex 8
I	Exam twist: instruction encoding budget	$k$ ko opcode bits ke saath mix karna	Ex 9
J	R0 degenerate storage	ek register store karta hai kuch nahi	Ex 10

Prerequisite building blocks Multiplexers and Decoders aur Datapath and ALU mein hain; timing row Pipeline Hazards par lean karti hai.

Worked Examples

Cell A — clean power of two

Worked example Example 1 — 32 registers ke liye address bits

Ek classic RISC CPU mein 32 registers hain. Ek register-name field ko kitne bits chahiye?

Forecast: aage padhne se pehle number guess karo. (Hint: 32 ko 1 tak pahunchane ke liye kitni baar half karte ho?)

Law likho: $k = ⌈ lo g_{2} N ⌉$ , yahan $N = 32$ . Yeh step kyun? $N$ mein se 1 cheez select karna exactly wahi karta hai jo ek address karta hai, aur $k$ bits $2^{k}$ cheezein distinguish karti hain — to hum $k$ nikalne ke liye usse invert karte hain.
$lo g_{2} 32$ compute karo. Halving: $32 \to 16 \to 8 \to 4 \to 2 \to 1$ yani 5 halvings, to $lo g_{2} 32 = 5$ . Yeh step kyun? $lo g_{2}$ literally count karta hai "1 se kitne doublings se $N$ tak pahunche" — aur $2^{5} = 32$ confirm karta hai.
$32$ ek power of 2 hai, isliye ceiling kuch change nahi karta: $k = 5$ .

Verify: $2^{5} = 32 = N$ . ✓ Bilkul enough patterns, koi waste nahi.

Cell B — power of two nahi (ceiling trap)

Cell C — degenerate single register

Cell D — total stored state (ports count nahi hote)

Cell E — superscalar port scaling

Worked example Example 5 — 1-wide se 2-wide issue mein jaana

Baseline file: $R = 2, W = 1$ . Ek 2-issue superscalar core ko ek cycle mein do adds run karne hain, har ek 2 reads + 1 write karta hai. Area law kitne factor se badh jaata hai?

Forecast: double kaam — double area? Guess karo.

Naye read ports: $2 ops \times 2 reads = 4$ , to $R = 4$ . Naye write ports: $2 \times 1 = 2$ , to $W = 2$ . Yeh step kyun? Ports = simultaneous accesses; do independent 2-read/1-write ops ko apne saare operands ek saath live chahiye.
Area ratio $= \frac{( R _{new} + W _{new} ) ^{2}}{( R _{old} + W _{old} ) ^{2}} = \frac{( 4 + 2 ) ^{2}}{( 2 + 1 ) ^{2}}$ . Yeh step kyun? Area law $A \propto (R + W)^{2}$ ka matlab sirf total port count matter karta hai; $N \cdot n$ cancel karne ke liye ratio lete hain.
$= \frac{36}{9} = 4$ .

Verify: $(4 + 2)^{2} = 36$ , $(2 + 1)^{2} = 9$ , $36/9 = 4$ . ✓ Issue width double karne se register-file area chaar guna ho gayi — yahi reason hai ki wide cores file ko banks mein split karte hain (dekho RISC vs CISC aur Pipeline Hazards).

Cell F — limiting case (kitni tezi se badhta hai?)

Cell G — read-during-write timing

Worked example Example 7 — usi cycle mein R5 padhna jab woh likha ja raha hai

Ek clock cycle mein, read port 1 R5 address karta hai jab write port R5 mein naya value store kar raha hota hai. Read port par kya aayega?

Forecast: old value, new value, ya "depend karta hai"?

Yahan koi arithmetic nahi hai — yeh ek timing policy question hai. Do policies list karo:
- Read-first: read MUX clock edge se pehle purana flip-flop value sample karta hai ⇒ old value.
- Write-first (internal forwarding): file incoming write data ko seedha read port par bypass karti hai ⇒ new value. Yeh step kyun? Read aur write dono "same cycle mein" hote hain, isliye cycle ke andar ka order ek design choice hai, fixed truth nahi.
Real pipelines mein ek forwarding/bypass MUX add karte hain taaki ek cycle baad wala dependent instruction fresh data dekh sake. Yeh step kyun? Uske bina, reader stale data paata hai — ek read-after-write data hazard (Pipeline Hazards).

Verify (sanity): stored state unambiguous hai — edge ke baad, R5 naya value hold karta hai chahe koi bhi policy ho. Sirf woh alag hota hai jo us cycle mein read wire par appear hua. ✓ Koi number compute nahi karna; answer hai "policy-dependent, aur forwarding hazard fix karta hai."

Cell H — real-world word problem

Cell I — exam twist: instruction encoding budget

Worked example Example 9 — kya teen register fields fit hote hain?

Ek ISA fixed 32-bit instruction word use karta hai. $N = 32$ registers ke saath, ek 3-operand instruction add rd, rs1, rs2 ko teen register names encode karne hain. Opcode ke liye kitne bits bachte hain?

Forecast: guess karo ki teen register fields kitne bits khate hain, phir subtract karo.

Har register field $k = lo g_{2} 32 = 5$ bits ka hai (Ex 1). Teen fields: $3 \times 5 = 15$ bits. Yeh step kyun? Har named operand ko apna $k$ -bit selector chahiye — left-hand law se address width.
Opcode bits bache $= 32 - 15 = 17$ bits. Yeh step kyun? Instruction word ek fixed budget hai; register fields aur opcode isko share karte hain.
Twist check: agar designer $N = 64$ ( $k = 6$ ) kar de, teen fields $3 \times 6 = 18$ bits cost karengi, opcode ke liye $32 - 18 = 14$ bachenge. Yeh step kyun? Yahi "zyada registers hamesha better hai" ka real cost hai (parent ka mistake box dekho) — har extra address bit opcode space se chhina jaata hai, har instruction mein.

Verify: $3 \times 5 = 15$ , $32 - 15 = 17$ ✓; aur $3 \times 6 = 18$ , $32 - 18 = 14$ ✓. Zyada registers ⇒ kam opcodes. Trade-off confirmed.

Cell J — R0 degenerate storage

Worked example Example 10 — R0 kitne flip-flops use karta hai?

RISC-V ka R0 hardwired to 0 hai: woh hamesha 0 read karta hai aur writes ignore karta hai. 32-register, 32-bit file mein, actual storage flip-flops kitne hain, aur R0 ka cost kya hai?

Forecast: kya $32 \times 32$ flip-flops hain, ya kam?

Naively, state $= N \cdot n = 32 \times 32 = 1024$ bits. Yeh step kyun? Cell-D formula assume karta hai ki har register real bits store karta hai.
Lekin R0 kuch nahi store karta — iska read line logic 0 se tied hai, koi flip-flops nahi bane. To real flip-flops $= (32 - 1) \times 32 = 31 \times 32 = 992$ . Yeh step kyun? Hardwired constant ko koi memory cell nahi chahiye; sirf address slot reserved hai.
R0 ka hardware cost: essentially zero flip-flops, phir bhi free mov, nop, aur constant-0 source milta hai.

Verify: $32 \times 32 = 1024$ ; $31 \times 32 = 992$ ; saved $= 1024 - 992 = 32$ flip-flops. ✓ Ek register ka storage saved aur synthetic instructions milte hain — sabse best wala degenerate case.

Active Recall

Recall Har trap kaun se matrix cell mein hai?

40 registers → address bits? ::: Cell B (ceiling): $⌈ lo g_{2} 40 ⌉ = 6$ .
Kya 3rd read port total stored bits change karta hai? ::: Nahi — Cell D: state sirf $N \cdot n$ hai.
4-issue vs 1-issue area factor? ::: Cell F: $16 \times$ , from $(12/3)^{2}$ .
Same-cycle read jab register write ho raha ho? ::: Cell G: policy-dependent; forwarding new value deta hai.
64 registers opcode space kyun hurt karte hain? ::: Cell I: $k$ badhkar 6 ho jaata hai, teen fields 18 bits cost karte hain, kam opcode bits bachte hain.

Connections

Register file organization — parent; yeh page iska worked-examples drill hai.
Multiplexers and Decoders — yahan har $k$ ke peeche read MUX / write decoder.
Datapath and ALU — kyun $R = 2, W = 1$ natural port shape hai.
Pipeline Hazards — Cell G ka read-during-write aur forwarding.
RISC vs CISC — Cell E/F splitting aur Cell I ka encoding budget.
Memory Hierarchy — kyun hum is state ko on-chip rakhne ki zaroorat samajhte hain.
5.1.04 Register file organization (Hinglish) — same material Hinglish mein.

Address bits to select 1 of 40 registers?

⌈ lo g_{2} 40 ⌉ = 6

bits.

Do read/write ports register file ke total stored bits change karte hain?

Nahi; stored bits

= N \cdot n

only. Ports area aur speed affect karte hain.

Area factor 1-issue (

R = 2, W = 1

) se 4-issue (

R = 8, W = 4

) file mein jaane par?

(12/3)^{2} = 16 \times

larger.

32×32-bit RISC-V file mein kitne storage flip-flops hain, given R0 hardwired hai?

31 \times 32 = 992

(R0 kuch store nahi karta).

32-bit word mein teen 5-bit register fields ke baad opcode bits kitni bachti hain?

32 - 15 = 17

bits.