Question bank — Register file organization

True — selecting 1 of $2^5=32$ registers needs exactly ==$\lceil {\log }_{2}32\rceil =5$ bits==. Fewer bits can't name every register; more bits waste opcode space. ::: True. ${\log }_{2}32=5$ is the minimum select width for the MUX and decoder; anything less leaves some registers unreachable.

::: False. Area scales as $(R+W{)}^2$, not linearly — extra ports add wires and stretch every cell in both dimensions, so cost grows super-linearly, not proportionally.

::: False. More registers widen the address field in every instruction, enlarge the read MUX and write decoder (slowing access), and add state to save on every context switch — it is costly on several fronts at once.

::: False. R0 holds no state to corrupt — it is hardwired to 0 and writes are silently discarded, so add r0, r0, r0 is a safe nop.

::: True for the stored bits: $N\cdot n=32\times 64=2048$. Ports add wiring and MUX/decoder logic but not stored state, so the flip-flop count is unaffected by $R$ or $W$.

different registers each cycle. ::: True — each read port is an independent $2^k$-to-1 MUX with its own select lines, so the two ports can address the same register or two different ones, freely.

::: True. One write port = one decoder routing data to exactly one register per clock edge; two simultaneous writes need $W=2$, which is why superscalar cores add write ports.

rs1 and rs2 we route both through the same multiplexer, one after the other." ::: Error: a single MUX outputs one value per select. Simultaneous reads need two independent MUXes (one per read port); serializing them would take two cycles and defeat single-cycle operand fetch.

::: Error: the decoder picks the line, but each decoded line is ANDed with a global WriteEnable. Without the enable being asserted, no register captures — so writes happen only when both the address decodes and the enable is high.

::: Error: it's $(4+2{)}^2/(2+1{)}^2=36/9=4\times$ larger, not 2×. The port count enters squared, so the "obvious" doubling drastically underestimates the real area growth.

::: Error: R0 has no flip-flop — its read line is tied to logic 0. It costs zero storage while buying free mov, nop, and a constant-0 source, so it's a saving, not a waste.

::: Error: it's the reverse. Reading is pick one of many onto a wire → a MUX; writing is route one wire to one of many → a decoder + enable.

::: Error: each added port grows every cell's area and parasitic capacitance, so the whole file gets bigger and slower on every access. The $(R+W{)}^2$ law makes 10 ports enormous — real designs bank or split the file instead.

$R=2,W=1$ the natural default rather than some other split? ::: A 2-operand instruction like add rd, rs1, rs2 reads two sources and writes one destination in a single cycle. The port count is chosen to match the ALU's operand shape, not picked arbitrarily.

::: One factor of $(R+W)$ is the number of wires crossing each cell; the other is that adding a port stretches each cell in both height and width (word-lines and bit-lines grow). Multiplying the two dimensions gives the square.

::: A monolithic file with many ports pays the $(R+W{)}^2$ penalty in full. Splitting into banks each with fewer ports keeps each bank cheap and fast, trading a routing/arbitration cost for a much smaller area explosion.

save opcode space? ::: A constant-0 source lets several operations reuse the existing ALU: mov rd, rs becomes add rd, rs, r0, nop becomes add r0, r0, r0. Fewer dedicated opcodes are needed because one free constant collapses them into add.

::: Each register needs a wider address field everywhere, a bigger/slower MUX and decoder, and more state to save on calls and context switches. Past ~16–32 the encoding and speed costs outweigh the reduction in memory traffic.

$N$ and $n$ but not on $R$ or $W$? ::: State lives in the flip-flops: $N$ registers × $n$ bits each. Ports are read/write access paths (wiring, MUXes, decoders) laid over that state — they change area and speed, never the amount stored.

::: It depends on the design: write-first (internal forwarding) returns the new value, read-first returns the old value. Pipelines add a bypass MUX so dependent instructions get the just-computed value and avoid a stale-data hazard.

same register in one cycle? ::: This is a write conflict — the outcome is undefined unless the design specifies priority. Hardware must either forbid it (via issue logic) or pick a fixed winner, since a flip-flop can capture only one value per edge.

::: $\lceil {\log }_{2}1\rceil =0$ bits — there's nothing to select, so no address field is needed. This is the degenerate boundary of the $\lceil {\log }_{2}N\rceil$ rule.

$N$ is not a power of two (say 20), how many address bits are needed? ::: $\lceil {\log }_{2}20\rceil =5$ bits, since 4 bits only reach 16. The remaining $32-20=12$ addresses are simply unused/reserved, which is why $N$ is usually chosen as a power of two.

::: Still 0. The write to R0 is discarded by construction, so R0 is always a reliable constant-0 source regardless of any preceding write instruction.

$W=0$ (zero write ports), what kind of "register file" do you have? ::: A read-only constant table — you can select and read values but never update them. It's a degenerate case: useful for hardwired constants or lookup tables, not for general-purpose working registers.