Register file organization: Question bank — Hinglish deep dive

5.1.4 · D5 · Hardware › Instruction Set Architecture (ISA) › Register file organization

Answers ke peechhe ki machinery ke liye Multiplexers and Decoders (reads aur writes kaise select hote hain), Datapath and ALU (ports exist kyun karte hain), aur Pipeline Hazards (read-during-write timing) ka sahara lo.

True or false — justify karo

Recall 32 registers wale register file ko hamesha 5-bit address field chahiye hota hai.

True — $2^{5} = 32$ registers mein se 1 select karne ke liye exactly == $⌈ lo g_{2} 32 ⌉ = 5$ bits== chahiye. Kam bits har register ko naam nahi de sakti; zyada bits opcode space waste karti hain. ::: True. $lo g_{2} 32 = 5$ MUX aur decoder ke liye minimum select width hai; isse kam kuch registers unreachable reh jaate hain.

Recall Read ports ki sankhya double karne se register file ka area double ho jaata hai.

::: False. Area $(R + W)^{2}$ ke hisaab se scale karta hai, linearly nahi — extra ports wires bhi add karte hain aur har cell ko dono dimensions mein stretch karte hain, isliye cost super-linearly badhti hai, proportionally nahi.

Recall Registers add karna free hai jab tak tumhare paas spare opcode bits hain.

::: False. Zyada registers har instruction mein address field ko wider banate hain, read MUX aur write decoder ko bada karte hain (access slow karte hain), aur har context switch par save karne ke liye state add karte hain — ye ek saath kaafi fronts par costly hai.

Recall RISC-V mein R0 par write karne se jo constant tha woh corrupt ho jaata hai.

::: False. R0 mein koi state hi nahi hai jo corrupt ho — yeh hardwired 0 hai aur writes silently discard ho jaati hain, isliye add r0, r0, r0 ek safe nop hai.

Recall 64-bit ke 32 registers store karne wale register file mein exactly 2048 flip-flops hote hain.

::: Stored bits ke liye True: $N \cdot n = 32 \times 64 = 2048$ . Ports wiring aur MUX/decoder logic add karte hain lekin stored state nahi, isliye flip-flop count $R$ ya $W$ se unaffected rehta hai.

Recall Do read ports ka matlab hai ki file har cycle mein do

alag registers read kar sakti hai. ::: True — har read port ek independent $2^{k}$ -to-1 MUX hai apne select lines ke saath, isliye dono ports ek hi register ya do alag registers ko freely address kar sakte hain.

Recall Single-write-port file kabhi bhi ek hi cycle mein do registers update nahi kar sakti.

::: True. Ek write port = ek decoder jo data ko exactly ek register par route karta hai per clock edge; do simultaneous writes ke liye $W = 2$ chahiye, isliye superscalar cores write ports add karte hain.

Error dhundho

Recall "

rs1 aur rs2 padhne ke liye hum dono ko ek hi multiplexer se route karte hain, ek ke baad ek." ::: Error: ek MUX ek value per select output karta hai. Simultaneous reads ke liye do independent MUXes chahiye (har read port ke liye ek); unhe serialize karne mein do cycles lagenge aur single-cycle operand fetch ki baat hi khatam ho jaegi.

Recall "Write decoder akela decide karta hai ki kaunsa register naya data capture kare."

::: Error: decoder line pick karta hai, lekin har decoded line ek global WriteEnable ke saath AND hoti hai. Enable assert na ho toh koi register capture nahi karta — isliye writes tab hoti hain jab dono address decode ho aur enable high ho.

Recall "2-read/1-write file se 4-read/2-write file pe jaana isse 2× bada banata hai."

::: Error: yeh $(4 + 2)^{2} / (2 + 1)^{2} = 36/9 = 4 \times$ bada hota hai, 2× nahi. Port count squared mein aata hai, isliye "obvious" doubling real area growth ko drastically underestimate karti hai.

Recall "R0 ek flip-flop waste karta hai jo useful data store kar sakta tha."

::: Error: R0 mein koi flip-flop nahi hai — iski read line logic 0 se tied hai. Yeh zero storage cost par free mov, nop, aur constant-0 source deta hai, isliye yeh waste nahi, balki saving hai.

Recall "Reads decoders se bani hoti hain aur writes multiplexers se."

::: Error: yeh ulta hai. Reading matlab many mein se ek ko wire par pick karo → MUX; writing matlab ek wire ko many mein se ek par route karo → decoder + enable.

Recall "Kyunki ports sirf wires hain, 10-read-port file theek hai — yeh sirf thodi badi hoti hai."

::: Error: har added port har cell ka area aur parasitic capacitance badhata hai, isliye poori file badi bhi hoti hai aur har access par slower bhi. $(R + W)^{2}$ law 10 ports ko enormous banata hai — real designs iske bajaye file ko bank ya split karte hain.

Why questions

Recall

$R = 2, W = 1$ natural default kyun hai, koi aur combination kyun nahi? ::: add rd, rs1, rs2 jaisi 2-operand instruction do sources padhti hai aur ek destination likhti hai ek hi cycle mein. Port count ALU ke operand shape se match karne ke liye choose kiya jaata hai, arbitrarily nahi.

Recall Area cost port count ko sum karne ki jagah square kyun karti hai?

::: $(R + W)$ ka ek factor har cell ko cross karne wale wires ki sankhya hai; doosra factor yeh hai ki ek port add karne se har cell dono height aur width mein stretch hota hai (word-lines aur bit-lines dono badhte hain). Dono dimensions multiply karne par square milta hai.

Recall Wide superscalar CPUs aksar register file ko banks mein split kyun karte hain?

::: Bahut saare ports wala ek monolithic file $(R + W)^{2}$ penalty poori tarah bharta hai. Banks mein split karne se har bank ke kam ports hote hain jo use cheap aur fast rakhte hain, aur ek much smaller area explosion ke badle routing/arbitration ka cost aata hai.

Recall Ek register ko zero se hardwire karna opcode space

bachata kyun hai? ::: Constant-0 source kai operations ko existing ALU se reuse karne deta hai: mov rd, rs ban jaata hai add rd, rs, r0, nop ban jaata hai add r0, r0, r0. Kam dedicated opcodes ki zaroorat padti hai kyunki ek free constant unhe add mein collapse kar deta hai.

Recall Hum memory accesses bilkul khatam karne ke liye registers add karte kyun nahi reh sakte?

::: Har register ko har jagah wider address field chahiye, ek bada/slower MUX aur decoder chahiye, aur calls aur context switches par save karne ke liye zyada state chahiye. ~16–32 ke baad encoding aur speed costs memory traffic mein kami se zyada ho jaate hain.

Recall Stored bits ki sankhya

$N$ aur $n$ par depend kyun karti hai lekin $R$ ya $W$ par nahi? ::: State flip-flops mein rehti hai: $N$ registers × $n$ bits each. Ports read/write access paths hain (wiring, MUXes, decoders) jo us state ke upar rakhe hote hain — yeh area aur speed change karte hain, stored amount kabhi nahi.

Edge cases

Recall Read port kya value return karta hai jab woh usi register ko read kare jo us cycle mein write ho rahi hai?

::: Yeh design par depend karta hai: write-first (internal forwarding) naya value return karta hai, read-first purana value return karta hai. Pipelines ek bypass MUX add karte hain taaki dependent instructions abhi-compute ki gayi value pa sakein aur stale-data hazard se bachen.

Recall Agar do write ports ek hi cycle mein

usi register ko target karein toh kya hota hai? ::: Yeh ek write conflict hai — outcome undefined hai jab tak design priority specify na kare. Hardware ko ya toh ise forbid karna hoga (issue logic ke zariye) ya ek fixed winner choose karna hoga, kyunki ek flip-flop per edge sirf ek value capture kar sakta hai.

Recall Sirf 1 register wali file ke liye minimum address width kya hai?

::: $⌈ lo g_{2} 1 ⌉ = 0$ bits — select karne ke liye kuch hai hi nahi, isliye koi address field ki zaroorat nahi. Yeh $⌈ lo g_{2} N ⌉$ rule ki degenerate boundary hai.

Recall Agar register count

$N$ power of two nahi hai (jaise 20), toh kitne address bits chahiye? ::: $⌈ lo g_{2} 20 ⌉ = 5$ bits, kyunki 4 bits sirf 16 tak pahunchti hain. Bache hue $32 - 20 = 12$ addresses simply unused/reserved hote hain, isliye $N$ usually power of two choose kiya jaata hai.

Recall R0 ka read kya return karta hai jab tumne us par nonzero value "likhi" ho?

::: Phir bhi 0. R0 par write by construction discard ho jaati hai, isliye R0 hamesha ek reliable constant-0 source hai chahe pehle koi bhi write instruction aai ho.

Recall

$W = 0$ (zero write ports) ke saath kaisa "register file" hota hai? ::: Ek read-only constant table — tum values select aur read kar sakte ho lekin update kabhi nahi kar sakte. Yeh ek degenerate case hai: hardwired constants ya lookup tables ke liye useful, general-purpose working registers ke liye nahi.

Connections

Register file organization — parent note jise ye traps stress-test karte hain.
Multiplexers and Decoders — reads MUXes kyun use karte hain aur writes decoders kyun.
Datapath and ALU — port count ALU ke operand shape se match kyun karta hai.
Pipeline Hazards — read-during-write aur write-conflict edge cases.
RISC vs CISC — register count instruction encoding ke against kaise trade karta hai.