Imagine you must design a CPU. Every instruction must be fetched, decoded, executed. Two roads:
CISC (e.g., x86): one instruction can do a lot (e.g., "load from memory, multiply, store back" in a single opcode). Instructions are variable length. Decoding is complex.
RISC (ARM): each instruction does one simple thing, all instructions are the same length, and only special load/store instructions touch memory.
WHY? Memory access has unpredictable latency (cache miss!). By separating "talk to memory" (LDR/STR) from "compute" (ADD/SUB), each instruction has a more uniform, predictable cost — again helping real-time guarantees.
WHY many registers? Because the ALU can't touch memory, you need plenty of "scratch" slots on-chip. More registers ⇒ fewer slow memory trips ⇒ faster & lower power.
Think of a CPU as a kitchen. ARM's rule is: chefs (the math part) can only cook with ingredients already on the counter (registers). If something's in the fridge (memory), one worker must fetch it to the counter first (LOAD), and put it back after (STORE). Because every recipe card is the same size and does one small step, the kitchen runs like a smooth assembly line — fast and using very little electricity. That's why ARM is in your phone and even in spaceships, where saving power and never getting confused about timing really matters.
ARM basically ek RISC architecture hai — matlab instructions chhote, simple aur fixed-length hote hain. Idea simple hai: hardware ko simple rakho, compiler ko mehnat karne do. Isi wajah se ARM chips bahut kam power kha kar bhi achhi speed dete hain. Yehi reason hai ki aapke phone se lekar satellites aur flight computers tak, sab jagah ARM milta hai — kyunki battery aur radiation-hardened budget mein "performance per watt" sabse zaruri cheez hai.
Sabse important rule hai load/store: ALU (jo math karta hai) sirf registers ke saath kaam karta hai. Agar value memory mein hai, to pehle LDR karke register mein laao, kaam karo, fir STR se wapas bhejo. Ye separation isliye hai taaki har instruction ka cost predictable rahe — memory access slow aur unpredictable hota hai, to usse alag rakha gaya.
Pipeline ko assembly line ki tarah samjho: jab ek instruction execute ho raha hai, doosra decode ho raha hai, teesra fetch ho raha hai. Isse roughly har clock cycle mein ek instruction complete hota hai. Formula yaad rakho: total time = (k+n−1)τ, aur speedup k ke kareeb pahuchta hai. Aur ARM ka ek special feature hai conditional execution (jaise ADDEQ) — chhoti if conditions ke liye branch lene ki zarurat nahi, jisse pipeline flush nahi hota aur timing predictable rehti hai. Aerospace mein yehi deterministic timing sabse badi cheez hai.
