Because the caller-saved registers are stacked by hardware, your ISR can be a normal C function — the compiler handles callee-saved (R4–R11) registers if you use them.
Hardware saves the current context (auto-stacks 8 registers) and jumps via the vector table to the ISR address, then unstacks on return.
On Cortex-M, does a lower or higher priority number win?
Lower number = higher priority (0 is most urgent).
Difference between preemption priority and sub-priority?
Preemption priority decides who can interrupt a running ISR; sub-priority only breaks ties between simultaneously-pending equal-preemption IRQs and never causes preemption.
If a chip implements N priority bits and assigns p to preemption, how many preempt and sub levels?
2^p preemption levels and 2^(N-p) sub-priority levels.
Define interrupt latency.
Time from the event asserting the interrupt to the ISR's first instruction executing.
What is the deterministic hardware latency on Cortex-M3/M4 with no wait states?
~12 cycles (stacking + vector fetch).
Why must ISRs be short?
While an ISR runs, equal/lower-priority interrupts are blocked, inflating their latency and risking missed deadlines/dropped data.
What does tail-chaining optimize?
Back-to-back pending interrupts skip the unstack+restack (~6 cycles instead of ~24).
Why must shared ISR/main variables be volatile?
To force the compiler to re-read them from memory each time instead of caching a stale value in a register.
Which 8 registers does Cortex-M auto-stack on interrupt entry?
R0–R3, R12, LR, PC, xPSR.
Name two things you should NEVER do inside an ISR.
Blocking/long operations and calling non-reentrant functions (e.g. malloc, printf).
What term increases latency from software masking?
t_blocked — time interrupts were disabled (critical section / BASEPRI / __disable_irq).
Recall Feynman: explain it to a 12-year-old
You're doing homework (main program). The kitchen has a smoke alarm (interrupt). When it beeps, you must drop your pencil exactly where it is, deal with the smoke (the ISR), then pick the pencil back up and keep writing the same word. The alarm beeping = the hardware event. "Dropping the pencel exactly where it is" = the CPU saving your registers. Some alarms are scarier than others (fire > microwave timer) — that's priority: a fire alarm interrupts you even while you're already answering the microwave. The time between the beep and you actually standing up is the latency — keep it small by not being in the middle of something you can't pause.
Dekho, interrupt ka matlab simple hai: ek hardware event (timer khatam, UART pe byte aaya, GPIO pin toggle) hone par CPU ko force kiya jaata hai ki apna current kaam ka context save kare aur ek special function — ISR — pe jump kare. Polling mein tum baar-baar check karte raho, CPU aur power waste hota hai; interrupt mein tum apna kaam karte raho aur "doorbell" bajne par hi react karo. Isse latency kam aur efficiency zyada.
NVIC decide karta hai ki agar do interrupt ek saath aaye to kaun jeetega. Yaad rakho — Cortex-M pe chhota number = zyada important (0 sabse top). Priority byte do hisson mein bantta hai: preemption priority (kaun kis running ISR ko beech mein rok sakta hai) aur sub-priority (sirf tie todne ke liye, preempt nahi karwati). Agar chip N bits implement karta hai aur tum p bits preemption ko de do, to 2p preempt levels aur 2N−p sub levels milte hain — total 2N hamesha same rehta hai.
Latency = event hone se ISR ki pehli instruction chalne tak ka time. Iska ek fixed hardware part hai (~12 cycles Cortex-M pe, stacking + vector fetch), aur ek software part — jab tumne __disable_irq() se interrupts band kiye the ya koi lambi same/higher ISR chal rahi thi. Isiliye golden rule: ISR chhoti rakho — flag clear karo, data uthao, ek flag set karo, return. Bhaari kaam main loop pe defer karo (ring buffer use karke).
Do galtiyan jo har beginner karta hai: (1) shared variable ko volatile na banana — compiler usse register mein cache kar leta hai aur while(!flag) infinite loop ban jaata hai; fix = volatile lagao. (2) ISR ke andar printf/lambi calculation karna — isse baaki interrupts ki latency badh jaati hai aur deadlines miss ho sakti hain. Mantra yaad rakho: "Zero is the hero, ISR rakho chhoti."
