Embedded Systems & Real-Time Software

Question 1 (12 marks)

(a) Nyquist rate = $2 \times 8.5\text{ kHz} = 17\text{ kHz}$ minimum (1). Real ADCs need a transition band for the anti-alias filter; sampling well above Nyquist (oversampling to 48 kHz) relaxes the analog filter's roll-off requirement and pushes aliasing away from the signal band (2).

(b) LSB $= V_{ref}/2^{12} = 3.3/4096 = 8.057\times10^{-4}$ V $\approx 0.806$ mV (2). Max quantisation error $= \pm\frac{1}{2}$ LSB $= 0.403$ mV (1).

(c) Folding about $f_s = 48$ kHz. $30$ kHz $> f_s/2 = 24$ kHz, so alias $= |f_s - f| = |48-30| = 18$ kHz (2). Since 18 kHz $>$ signal band (8.5 kHz), it corrupts nothing in-band here but confirms aliasing occurs; the alias appears at 18 kHz (1).

(d) DMA is better: continuous, periodic samples at 48 kHz would generate 48 000 interrupts/s, imposing high ISR overhead/latency (2). DMA moves each converted sample peripheral-to-memory without CPU intervention, interrupting only on buffer-full (1).

Question 2 (14 marks)

(a) Compare bit-by-bit; lowest binary value (most dominant/0 bits early) wins.

bit#: 1 2 3 4 5 6 7 8 9 10 11
A   : 1 0 0 1 1 0 0 0 0  1  1
B   : 1 0 0 1 0 1 0 1 1  1  1
C   : 1 0 0 1 1 0 0 0 0  0  1

Bits 1–4 identical (1). At bit 5: A=1, B=0, C=1. B sends dominant 0, so A and C would lose — but wait, A and C both send recessive 1 while B sends 0 (dominant). Bus reads dominant. A and C see mismatch and drop out at bit 5 (2). B continues alone and wins arbitration (2).

(Full credit: winner = Node B, losers A & C drop out at bit position 5.)

(b) Total bits $\approx 11 + 6 + 24 + 15 + 13 = 69$ bits (2). Time $= 69 / (500\times10^3) = 138\ \mu s$ (2).

(c) Arbitration is non-destructive: a node transmitting recessive that reads dominant yields immediately without losing data; the highest-priority (lowest ID) frame always proceeds bit-uninterrupted (2). A lower-priority frame can delay a pending high-priority frame by at most the currently-in-progress frame time — bounded latency, essential for deterministic aerospace timing (1).

(d) Any of: bit monitoring, bit-stuffing check, CRC check, form check, ACK check (1). When the Transmit Error Counter exceeds 255, the node enters the bus-off state and removes itself from the bus (stops transmitting) (1).

Question 3 (14 marks)

(a) L holds mutex → H preempts L → H blocks on mutex (waiting for L). M (priority 3) becomes ready; since M > L and H is blocked, scheduler runs M, not L (2). M keeps running (CPU-bound), so L never gets CPU to finish and release the mutex, so H stays blocked (2). It is unbounded because any number of medium-priority tasks can keep running indefinitely, so the delay to H has no bound related to L's critical section length (1).

(b) With priority inheritance, when H blocks on the mutex held by L, L's priority is temporarily raised to H's priority (5) (2). Now L outranks M, so M cannot preempt L; L runs, finishes its critical section, releases the mutex (1). On release, L reverts to its original priority (1), and H immediately acquires the mutex and runs. Inversion is bounded by L's critical-section length.

(c) Use a mutex (xSemaphoreCreateMutex) which supports priority inheritance (1). Do not use a binary semaphore for mutual exclusion — it has no inheritance and no ownership (1).

(d) Pass priority 5 for H (valid range 0…configMAX_PRIORITIES-1 = 0…5) (2). The idle task runs at priority 0, the lowest, so it only runs when no other task is ready (1).

Question 4 (10 marks)

(a) 10-bit resolution needs 1024 counts, so ARR $= 1023$ (period = 1024 counts) (1). Timer tick freq needed $= 20\text{ kHz} \times 1024 = 20.48$ MHz (1). Prescaler divides 80 MHz: $80\text{ MHz}/20.48\text{ MHz} = 3.906$ (1). Not an integer → exact 20 kHz with full 10-bit resolution is not achievable simultaneously (1). Choosing PSC=3 (divide-by-4) → tick = 20 MHz, with ARR=999 gives exactly 20 kHz but only ~10-bit (1000 steps). Comment: trade resolution vs exactness; PSC=0, ARR=3999 gives exact 20 kHz with 4000 steps (>10 bit). Accept any correct reasoned choice (1).

(b) With ARR=1023 (1024 steps), 35% → CCR $= 0.35 \times 1024 = 358.4 \Rightarrow 358$ (2). (If using ARR=3999: CCR = 1400.)

(c) Input capture latches the timer count on each signal edge; period = difference between successive captured counts, frequency = timer_clock/(count difference) (2). Error source: timer resolution/quantisation, or jitter/prescaler granularity, or missed edges at high frequency (1).

Question 5 (10 marks)

(a) Three identical lanes compute the same output from the same inputs; a majority voter outputs the value agreed by ≥2 lanes (2). If one lane disagrees, the voter masks it (outputs the majority) and the faulty lane can be flagged/isolated, system continues correctly (1).

(b) Fail-safe: on fault, transition to a safe (often inactive/de-energised) state — acceptable when a safe state exists (1.5). Fail-operational: continue delivering full function despite a fault (1). For a UAV primary flight loop with no manual backup, dropping to a safe passive state = crash, so fail-operational is required (0.5).

(c) Roles: (i) detect software hang/deadlock and reset the MCU; (ii) detect a task overrunning/missing its deadline (1). "Feeding" = periodically resetting the watchdog counter before it expires; it must be done from a healthy point that proves the whole system is alive (e.g. after a supervisor confirms all critical tasks ran) and not blindly from a timer ISR or tight loop that could keep running while the app is dead (1).

(d) Any one: dynamic allocation risks non-deterministic timing, heap fragmentation, allocation failure/out-of-memory at runtime, and unpredictable WCET — all unacceptable in safety-critical code (2).

[
  {"claim":"ADC LSB voltage = 3.3/4096 ≈ 0.806 mV","code":"lsb = Rational(33,10)/4096; result = abs(float(lsb) - 0.0008057) < 1e-6"},
  {"claim":"Alias of 30kHz at fs=48kHz is 18kHz","code":"fs=48; f=30; alias=abs(fs-f); result = alias==18"},
  {"claim":"CAN frame ~69 bits at 500kbit/s = 138us","code":"bits=11+6+24+15+13; t=bits/500000; result = bits==69 and abs(t-138e-6)<1e-9"},
  {"claim":"PWM: 80MHz/(20kHz*1024) not integer","code":"ratio = 80e6/(20000*1024); result = abs(ratio-3.90625)<1e-6 and ratio != int(ratio)"},
  {"claim":"35% of 1024 steps = 358","code":"ccr = int(0.35*1024); result = ccr==358"}
]