Interrupts — ISR design, NVIC priority, interrupt latency: Worked examples

The scenario matrix

Before any numbers, let us list every kind of situation these formulas must survive. Each row is one case class; the worked examples below are tagged with the row they hit.

#	Case class	The question it answers	Degenerate / edge form
A	Priority split ( $2^{p}$ , $2^{N - p}$ )	How many preempt vs sub levels?	$p = 0$ (no preemption) and $p = N$ (no sub-levels)
B	Preemption decision	Does IRQ-X interrupt running IRQ-Y?	Equal preempt → no preemption
C	Sub-priority tiebreak	Two pending at once, equal preempt — who runs first?	Equal sub too → lower IRQ number wins
D	Latency, normal	Time to first ISR instruction	Event fires while IRQs masked (worst case)
E	Latency, tail-chaining	Back-to-back IRQs, cost saved	Limiting case: many queued IRQs
F	Deadline / real-world	Do we drop a UART byte?	Zero slack (exactly meets)
G	Exam twist	Combine grouping + latency + a trap	"higher number = more urgent" trap

The formulas we lean on, restated so no symbol is unearned:

Case A — the priority split, including both degenerate ends

Case B & C — preemption vs tiebreak, all sign/order combinations

Remember the golden trap: lower numeric priority = more urgent. We test every ordering.

Case D — latency, normal and worst-case (masked)

Case E — tail-chaining and its limiting behaviour

Case F — real-world word problem (deadline / dropped byte)

Worked example

F1 (UART at risk). A UART receives bytes at 115200 baud, 8N1 framing (10 bits per byte). Its RX interrupt must be serviced before the next byte overwrites the register. Your worst-case latency (from D1) is $620 ns$ , and the ISR itself takes $200 ns$ . Do you drop bytes?

Forecast: guess YES or NO before computing the byte period.

Time per byte $= \frac{10 bits}{115200 bits/s} = 8.68 \times 1 0^{- 5} s = 86.8 μ s$ . Why 10 bits? 8N1 = 1 start + 8 data + 1 stop bit.
Time budget to service one byte = one byte period $= 86.8 μ s$ .
Worst service time $= t_{lat,worst} + t_{ISR} = 620 + 200 = 820 ns = 0.82 μ s$ .
Slack $= 86.8 - 0.82 = 85.98 μ s > 0$ ⇒ no dropped bytes, with huge margin.

Verify: $0.82 ≪ 86.8$ ✔; ratio $0.82/86.8 \approx 0.94%$ CPU used per byte — comfortably meets the deadline. This is exactly why a short ISR + ring buffer (see Ring Buffers / FIFO Queues) keeps deadlines safe.

Case G — the exam twist (grouping + latency + the trap)

Worked example

G1 (combined trap question). "IRQ-P has priority number $0$ , IRQ-Q has priority number $5$ . A student says 'Q is more important because 5 > 0.' Config $N = 4$ , $p = 4$ (all preempt). Q is running; P becomes pending. (a) Who is really more urgent? (b) Does P preempt Q? (c) If $f_{clk} = 100$ MHz and P's stacking is the 12-cycle hardware part with no masking, when does P's first instruction run?"

Forecast: spot the trap in the student's claim before step 1.

(a) On Cortex-M, lower number = higher urgency, so P (0) is more urgent than Q (5). The student's "5>0" reasoning is the classic inverted-scale mistake.
(b) $p = 4$ ⇒ all bits are preempt, sub levels $= 2^{0} = 1$ . Preempt numbers $0 < 5$ ⇒ P preempts Q. Q is stacked, resumes after P.
(c) No masking, hardware part $= 12$ cycles, $= 12 \times 10 = 120 ns$ to P's first instruction (Q's current instruction assumed already at an interruptible point).

Verify: P first instr at $120 ns$ ; $0 < 5$ confirms P urgent and preempting. Trap correctly rejected.

Recall Self-test — reveal after answering

With $N = 4$ , $p = 0$ , how many things can preempt a running ISR? ::: Preempt levels $= 2^{0} = 1$ , so none — fully non-nested. Two IRQs equal preempt, equal sub, numbers 12 and 30 — who runs first? ::: IRQ 12 (lower IRQ number is the final tiebreak). Worst-case latency at 100 MHz with 12 fixed + 50 masked cycles? ::: $62 \times 10 ns = 620 ns$ . Tail-chaining saving for one B→C transition (24 naive vs 6)? ::: $18$ cycles $= 180 ns$ ( $75%$ ). One byte time at 115200 baud, 8N1? ::: $10/115200 \approx 86.8 μ s$ .

Worked examples — Interrupts — ISR design, NVIC priority, interrupt latency