Interrupts — ISR design, NVIC priority, interrupt latency: Worked examples

5.5.7 · D3 · Coding › Embedded Systems & Real-Time Software › Interrupts — ISR design, NVIC priority, interrupt latency

Scenario matrix

Koi bhi number se pehle, aao hum har tarah ki situation list karte hain jinse ye formulas survive karni chahiye. Har row ek case class hai; neeche ke worked examples us row ke saath tagged hain jise woh hit karte hain.

#	Case class	Yeh kaunsa sawaal answer karta hai	Degenerate / edge form
A	Priority split ( $2^{p}$ , $2^{N - p}$ )	Kitne preempt vs sub levels hain?	$p = 0$ (no preemption) aur $p = N$ (no sub-levels)
B	Preemption decision	Kya IRQ-X, running IRQ-Y ko interrupt karta hai?	Equal preempt → no preemption
C	Sub-priority tiebreak	Ek saath do pending, equal preempt — pehle kaun run karta hai?	Equal sub bhi → lower IRQ number jeets hai
D	Latency, normal	ISR ki pehli instruction tak ka time	Event fire hota hai jabki IRQs masked hain (worst case)
E	Latency, tail-chaining	Back-to-back IRQs, bacha hua cost	Limiting case: bahut saare queued IRQs
F	Deadline / real-world	Kya hum ek UART byte drop kar dete hain?	Zero slack (exactly meets)
G	Exam twist	Grouping + latency + ek trap combine karo	"higher number = more urgent" trap

Jinhe hum rely karte hain woh formulas, dobara state karte hain taaki koi symbol earn kiye bina na ho:

Case A — priority split, dono degenerate ends including

Case B & C — preemption vs tiebreak, sare sign/order combinations

Yaad rakho golden trap: lower numeric priority = more urgent. Hum har ordering test karte hain.

Case D — latency, normal aur worst-case (masked)

Worked example

D1 (worst-case latency with a critical section). $f_{clk} = 100 MHz$ . Fixed hardware part $= 12$ cycles. Tumhara longest __disable_irq() critical section $50$ cycles tak chalta hai. Event mask hone ke just baad fire hota hai. Worst-case latency ns mein find karo.

Forecast: ye sirf 12 cycles nahi hai — ns figure guess karo.

Ek cycle $= 1/ (100 \times 1 0^{6}) = 10 ns$ . Kyun? humne ns mein numeric answer assert kiya, isliye cycles→time convert karo.
$t_{blocked} = 50$ cycles: event ko stacking start hone se pehle poora masked window wait karna hoga. Ise kyun add karte hain? masked hone par, NVIC request ko pending hold karta hai — koi stacking nahi.
Total cycles $= t_{blocked} + hardware = 50 + 12 = 62$ .
$t_{lat,worst} = 62 \times 10 ns = 620 ns$ .

Verify: units: cycles $\times$ (ns/cycle) $=$ ns ✔. Numeric: $620 ns = 0.62 μ s$ , 100 MHz MCU ke liye plausible.

Case E — tail-chaining aur uska limiting behaviour

Case F — real-world word problem (deadline / dropped byte)

Worked example

F1 (UART at risk). Ek UART bytes 115200 baud par receive karta hai, 8N1 framing (10 bits per byte). Uska RX interrupt service hona chahiye agli byte register overwrite karne se pehle. Tumhara worst-case latency (D1 se) $620 ns$ hai, aur ISR khud $200 ns$ leta hai. Kya tum bytes drop karte ho?

Forecast: byte period compute karne se pehle YES ya NO guess karo.

Time per byte $= \frac{10 bits}{115200 bits/s} = 8.68 \times 1 0^{- 5} s = 86.8 μ s$ . 10 bits kyun? 8N1 = 1 start + 8 data + 1 stop bit.
Ek byte service karne ka time budget = ek byte period $= 86.8 μ s$ .
Worst service time $= t_{lat,worst} + t_{ISR} = 620 + 200 = 820 ns = 0.82 μ s$ .
Slack $= 86.8 - 0.82 = 85.98 μ s > 0$ ⇒ koi dropped bytes nahi, bahut bade margin ke saath.

Verify: $0.82 ≪ 86.8$ ✔; ratio $0.82/86.8 \approx 0.94%$ CPU used per byte — deadline comfortably meet karta hai. Yahi reason hai ki ek short ISR + ring buffer (dekho Ring Buffers / FIFO Queues) deadlines safe rakhta hai.

Case G — the exam twist (grouping + latency + the trap)

Worked example

G1 (combined trap question). "IRQ-P ka priority number $0$ hai, IRQ-Q ka priority number $5$ hai. Ek student kehta hai 'Q zyada important hai kyunki 5 > 0.' Config $N = 4$ , $p = 4$ (all preempt). Q run ho raha hai; P pending ho jaata hai. (a) Actually zyada urgent kaun hai? (b) Kya P, Q ko preempt karta hai? (c) Agar $f_{clk} = 100$ MHz aur P ka stacking 12-cycle hardware part hai bina masking ke, P ki pehli instruction kab run karta hai?"

Forecast: step 1 se pehle student ke claim mein trap spot karo.

(a) Cortex-M par, lower number = higher urgency, isliye P (0), Q (5) se zyada urgent hai. Student ki "5>0" reasoning classic inverted-scale mistake hai.
(b) $p = 4$ ⇒ saare bits preempt hain, sub levels $= 2^{0} = 1$ . Preempt numbers $0 < 5$ ⇒ P, Q ko preempt karta hai. Q stack ho jaata hai, P ke baad resume hota hai.
(c) Koi masking nahi, hardware part $= 12$ cycles, $= 12 \times 10 = 120 ns$ P ki pehli instruction tak (Q ki current instruction already ek interruptible point par assumed).

Verify: P pehli instr $120 ns$ par; $0 < 5$ confirm karta hai P urgent hai aur preempt kar raha hai. Trap correctly reject kiya gaya.

Recall Self-test — answer karne ke baad reveal karo

$N = 4$ , $p = 0$ ke saath, kitni cheezein running ISR ko preempt kar sakti hain? ::: Preempt levels $= 2^{0} = 1$ , isliye koi nahi — fully non-nested. Do IRQs equal preempt, equal sub, numbers 12 aur 30 — pehle kaun run karta hai? ::: IRQ 12 (lower IRQ number final tiebreak hai). 100 MHz par worst-case latency 12 fixed + 50 masked cycles ke saath? ::: $62 \times 10 ns = 620 ns$ . Ek B→C transition ke liye tail-chaining saving (24 naive vs 6)? ::: $18$ cycles $= 180 ns$ ( $75%$ ). 115200 baud, 8N1 par ek byte ka time? ::: $10/115200 \approx 86.8 μ s$ .

Worked examples — Interrupts — ISR design, NVIC priority, interrupt latency

Scenario matrix

Case A — priority split, dono degenerate ends including

Case B & C — preemption vs tiebreak, sare sign/order combinations

Case D — latency, normal aur worst-case (masked)

Case E — tail-chaining aur uska limiting behaviour

Case F — real-world word problem (deadline / dropped byte)

Case G — the exam twist (grouping + latency + the trap)

See also