Intuition The ONE core ideaA computer normally runs your program line by line, but sometimes an event in the outside world (a button, a timer, a byte arriving) is too urgent to wait for your loop to notice it. An interrupt is a doorbell wired straight into the CPU: the hardware slams your program on pause, jumps to a special little function to deal with the event, then puts your program back exactly where it was — and the whole art is making that pause fast, safe, and correctly ordered .
This page assumes nothing . Before you read the parent topic , you must be fluent in every word and symbol it throws at you. We build each one from a picture.
Intuition The program counterPicture a long list of instructions in memory, each at its own numbered address. The CPU has a single finger pointing at "the instruction I am doing right now." That finger has a name.
Definition Program Counter — the symbolP C
P C address of the current (or next) instruction .Picture: the moving finger in the figure above, sliding down the instruction list.Why the topic needs it: an interrupt is defined as "make the finger jump somewhere else, then come back." You cannot talk about jumping without naming what jumps — that's P C
Normally the finger just steps forward: address, address+1, address+2. A jump means the finger suddenly lands on a different address. An interrupt is a jump the hardware forces, not one you wrote.
Intuition Why registers existReading from main memory (RAM) is slow. So the CPU keeps a handful of ultra-fast slots right next to its arithmetic unit. It shovels values into these slots, computes, and shovels results back. These slots are registers .
Definition Registers — the symbolsR 0 R 12 L R P C x P S R
Register ::: a named, super-fast storage cell inside the CPU (holds one word — 32 bits on Cortex-M).R 0 R 12 L R where to go back to after a function call.x P S R Picture: a row of small labelled boxes; the figure below shows them.Why the topic needs it: when the CPU is yanked away to an interrupt, the values in these boxes are the program's thoughts mid-sentence . If they get clobbered, the interrupted program becomes corrupted nonsense when it resumes. So the topic constantly talks about saving and restoring exactly these boxes.
Definition Caller-saved vs callee-savedThe parent note says hardware auto-saves R 0 R 3 R 12 L R P C x P S R caller-saved set) and the compiler handles R 4 R 11 callee-saved ) if used.
Caller-saved ::: registers a function is free to trample, so whoever called must save them first if it cares. Hardware does this for interrupts → 8 words.Callee-saved ::: registers a function must preserve, so if the ISR uses them, the compiler inserts push/pop.Why: this split is exactly why "an ISR can be a normal C function" — the caller-saved half is free, the callee-saved half the compiler already knows how to protect.
Intuition A stack of platesWhen you interrupt someone mid-task, you scribble their current state on a note and stack it on a pile. To resume, you take the top note back. Newest saved, first restored — "Last In, First Out."
Definition The stack and the symbolS P
Stack ::: a region of RAM used LIFO (Last In, First Out) to temporarily park values.Push ::: place a value on top. Pop ::: remove the top value.S P Picture: the growing/shrinking pile of plates above.Why the topic needs it: the parent's "stacking = hardware pushes 8 registers" and "unstacking " on exit are literally push-then-pop on this stack. The 8 saved registers are the program's parked context.
Recall Why LIFO and not a queue?Interrupts can nest (an interrupt inside an interrupt). The most recently interrupted context must resume first — that is exactly LIFO.
Which end of the stack is touched on both push and pop? ::: The top, tracked by S P
Definition Function call vs interrupt call
Function call ::: your code asks to run another chunk, saving a return address in L R ISR (Interrupt Service Routine) ::: the hardware forces a jump to a chunk, saving context on the stack, then coming back.Why the topic needs it: the parent's one-sentence picture — "an interrupt is a hardware-triggered function call the CPU is forced to make" — only makes sense once you know an ordinary function call is a voluntary "jump and come back." The interrupt is the involuntary cousin.
Intuition The device that raises its handA peripheral is a hardware block beside the CPU — a timer, a UART (serial port), a GPIO pin. When its event happens, it raises a wire (the interrupt line ) and sets a flag bit saying "it was me."
Definition Peripheral, interrupt line, flag, pending
Peripheral ::: an on-chip device that generates events (timer expiry, byte received, pin change).Interrupt line / request (IRQ) ::: the electrical signal a peripheral asserts to say "attend to me."Flag ::: a status bit inside the peripheral that stays set until you clear it, recording that the event happened.Pending ::: the NVIC's note that an IRQ is waiting to be serviced but hasn't run yet.Why the topic needs it: "clear the interrupt flag early" and "NVIC marks it pending " both live here. If you never clear the flag, the peripheral keeps re-raising its hand → the ISR fires forever.
Intuition A receptionist with a phone bookMany peripherals can raise their hands at once. Something must decide who goes first and which function to call . That something is the NVIC . Its phone book — "IRQ number → address of the function to run" — is the vector table .
Definition NVIC and vector table
NVIC (Nested Vectored Interrupt Controller) ::: the Cortex-M peripheral that receives IRQs, ranks them by priority , allows nesting (higher priority preempts a running lower-priority ISR), and tells the CPU where to jump.Vector table ::: an array in memory; entry k k Vectored ::: "the controller already knows the jump address" (looks it up in the table) — no software search needed.Why the topic needs it: every later idea (priority grouping, latency, tail-chaining) is a behaviour of the NVIC . And "load the ISR address from the vector table into P C
2 n
2 n n Picture: each extra bit doubles the number of options — a branching tree.Why the topic needs it: priority levels are counted this way. "N 2 N 2 p × 2 N − p
Worked example Warm-up conversionA critical section masks interrupts for 50 cycles at 100 MHz. How long is that?
50 × 10 ns = 500 ns . 120 ns 620 ns
Definition Masking / disabling interrupts
Mask ::: temporarily tell the CPU "ignore (delay) interrupts." Done with __disable_irq() or by raising BASEPRI (a threshold: block anything less urgent than a chosen level).Critical section ::: a short span of code where interrupts are masked so a shared variable isn't half-updated when the ISR barges in.Picture: a mute button on the doorbell — the pizza still arrives, but you don't hear it until you unmute.Why the topic needs it: masking is the software-controllable part of latency (t blocked atomic .
volatile and atomic
volatile ::: a keyword telling the compiler "this variable can change behind your back (an ISR writes it) — re-read it from memory every time, never cache it in a register."Atomic ::: an update that cannot be interrupted halfway; either fully done or not started.Why the topic needs it: these two prevent the classic ISR-vs-main-loop bugs (infinite while(!flag) and torn reads).
Program Counter - the moving finger
Registers R0 to R12 LR xPSR
Stack and SP - LIFO parking
ISR - forced function call
Peripherals flags IRQ lines
Vector table - address phone book
Cycles and clock frequency
Test yourself — if any answer is fuzzy, re-read that section before the parent note.
What does P C The address of the current instruction; hardware saves it and loads the ISR's address so the finger jumps.
Name the 8 registers the Cortex-M auto-stacks. R 0 R 3 R 12 L R P C x P S R
Why LIFO (a stack) and not a queue for saved context? Nested interrupts must resume most-recently-interrupted first — Last In, First Out.
What is a "flag" and why must an ISR clear it early? A peripheral status bit recording the event; if not cleared it keeps re-asserting the IRQ → the ISR re-enters forever.
What does the vector table map? IRQ number → the memory address of that interrupt's ISR.
How many levels do N 2 N 2 p 2 N − p
Convert 12 cycles to time at 100 MHz. 12 × 10 ns = 120 ns
What does volatile force the compiler to do? Re-read the variable from memory every access instead of caching it in a register.
What does masking (disabling) interrupts buy you, and what does it cost? Buys atomic access to shared data; costs added interrupt latency (t blocked
Next: with every symbol earned, read the parent topic . Related foundations you may want alongside: Polling vs Interrupt-driven I/O , Concurrency & Race Conditions , Ring Buffers / FIFO Queues , ARM Cortex-M Architecture , Real-Time Scheduling & Deadlines , Power Management & Sleep Modes .
