Interrupts — ISR design, NVIC priority, interrupt latency: Foundations

5.5.7 · D1 · Coding › Embedded Systems & Real-Time Software › Interrupts — ISR design, NVIC priority, interrupt latency

Yeh page kuch bhi assume nahi karta. parent topic padhne se pehle, aapko uske har word aur symbol mein fluent hona chahiye. Hum har ek ko ek picture se build karte hain.

1. CPU actually kya kar raha hai (the moving finger)

Figure — Interrupts — ISR design, NVIC priority, interrupt latency

Normally finger bas aage badhti hai: address, address+1, address+2. Ek jump matlab finger achanak kisi alag address par land karti hai. Interrupt ek aisa jump hai jo hardware force karta hai, koi aapne likha nahi.

2. Registers — CPU ka tiny scratchpad

Definition Registers — symbols

$R 0$ – $R 12$ , $L R$ , $P C$ , $x P S R$

Register ::: CPU ke andar ek named, super-fast storage cell (ek word hold karta hai — Cortex-M par 32 bits).
$R 0$ – $R 12$ ::: general-purpose scratch slots aapke numbers ke liye.
$L R$ (Link Register) ::: "return address" hold karta hai — kahan wapas jana hai function call ke baad.
$x P S R$ (Program Status Register) ::: status flags hold karta hai (kya last result zero tha? negative? kya overflow hua?).
Picture: chhote labelled boxes ki ek row; neeche figure unhe dikhata hai.
Topic ko kyun chahiye: jab CPU ko interrupt ke liye yanked away kiya jata hai, in boxes mein values program ke mid-sentence thoughts hain. Agar yeh clobber ho jayein, toh interrupted program resume hone par corrupted nonsense ban jata hai. Isliye topic baar baar in exact boxes ko save aur restore karne ki baat karta hai.

3. Stack — jahan saved context park hota hai

Recall LIFO kyun aur queue kyun nahi saved context ke liye?

Interrupts nest ho sakte hain (ek interrupt ke andar ek interrupt). Sabse recently interrupted context pehle resume hona chahiye — yeh exactly LIFO hai. Stack ke kis end ko push aur pop dono par touch kiya jata hai? ::: Top, $S P$ dwara track kiya gaya.

4. Functions aur "jump and come back" pattern

5. Peripherals, flags, aur interrupt line

6. NVIC aur vector table — traffic controller

7. Numbers jo aapko padhne aane chahiye: powers of two aur cycles

8. Masking — mute button

Prerequisite map

Equipment checklist

Khud test karo — agar koi bhi jawab fuzzy lage, toh parent note se pehle woh section dobara padho.

P C

kya hold karta hai, aur interrupt ke dauran uske saath kya hota hai?

Current instruction ka address; hardware ise save karta hai aur ISR ka address load karta hai taaki finger jump kare.

Cortex-M ke 8 auto-stacked registers ke naam batao.

R 0

–

R 3

R 12

L R

P C

x P S R

Saved context ke liye LIFO (stack) kyun aur queue kyun nahi?

Nested interrupts ko most-recently-interrupted pehle resume karna chahiye — Last In, First Out.

"Flag" kya hai aur ISR ko ise early kyun clear karna chahiye?

Peripheral status bit jo event record karta hai; clear na karne par woh IRQ baar baar assert hoti rehti hai → ISR bar bar re-enter karta hai.

Vector table kya map karta hai?

IRQ number → us interrupt ke ISR ka memory address.

N

implemented priority bits kitne levels dete hain?

2^{N}

total, split

2^{p}

preempt ×

2^{N - p}

sub.

100 MHz par 12 cycles ko time mein convert karo.

12 \times 10 ns = 120 ns

volatile compiler ko kya force karta hai?

Variable ko register mein cache karne ki bajaye har access par memory se re-read karna.

Interrupts mask (disable) karna aapko kya deta hai, aur uski kya cost hai?

Shared data tak atomic access milti hai; cost hai added interrupt latency (

t_{blocked}

Next: har symbol earn karne ke baad, parent topic padho. Related foundations jo aap saath rakhna chahein: Polling vs Interrupt-driven I/O, Concurrency & Race Conditions, Ring Buffers / FIFO Queues, ARM Cortex-M Architecture, Real-Time Scheduling & Deadlines, Power Management & Sleep Modes.