Embedded Systems & Real-Time Software

Q1. (3 marks) Any two valid differences (1.5 marks each):

• Cortex-M0 uses the ARMv6-M architecture with a mostly Thumb/Thumb-2 subset; Cortex-M4 uses ARMv7-M with the full Thumb-2 instruction set. (1.5)
• Cortex-M4 includes a hardware single-cycle DSP instruction set (MAC/SIMD) and an optional FPU; Cortex-M0 does not. (1.5)
• (Also acceptable: M4 has more NVIC priority bits, higher pipeline/performance, MPU option.) Why: M0 is minimal/low-power; M4 adds DSP+FPU for signal processing.

Q2. (3 marks)

• (a) Switch open: pull-up holds the pin high → reads logic 1 / high. (1.5)
• (b) Switch closed (to ground): pin pulled to ground through the switch → reads logic 0 / low. (1.5) Why: the pull-up defines the default state; closing to ground overrides it (active-low).

Q3. (5 marks) (a) One count period $= 1/16\text{MHz} = 62.5\ \text{ns}$. With 1000 counts: $T = 1000 \times 62.5\ \text{ns} = 62.5\ \mu\text{s}$ (2) $f = 1/T = 16\times10^6 / 1000 = 16\ \text{kHz}$ (1) (b) Duty cycle $= \dfrac{\text{CCR}}{\text{ARR}+1} = \dfrac{250}{1000} = 0.25 = \mathbf{25\%}$. (2)

Q4. (5 marks) (a) Nyquist: sampling rate must be at least twice the highest frequency component to avoid aliasing → $f_s \ge 2 \times 4\ \text{kHz} = \mathbf{8\ \text{kHz}}$. (2) (b) Resolution $= \dfrac{V_{ref}}{2^n} = \dfrac{3.3}{2^{12}} = \dfrac{3.3}{4096} \approx 8.06\times10^{-4}\ \text{V} \approx \mathbf{0.806\ \text{mV/LSB}}$. (3)

Q5. (6 marks — 2 marks per interface, or ~0.67 per correct cell)

Q6. (4 marks)

• CAN uses bitwise arbitration on the identifier field during the arbitration phase. (1)
• The bus is wired-AND: a dominant bit (logical 0) overrides a recessive bit (logical 1). (1)
• Each node transmits its ID and monitors the bus; a node that sends recessive but reads dominant loses and backs off (non-destructive arbitration). (1)
• The lower numeric identifier wins (more dominant/0 bits), giving it higher priority. (1)

Q7. (4 marks, 1 each)

• (a) Context switch: saving the current task's CPU register/state and restoring another task's state so the scheduler can switch execution between tasks.
• (b) Preemption: a higher-priority task interrupting and taking the CPU from a currently running lower-priority task before it finishes.
• (c) Mutex: a locking primitive providing mutual exclusion so only one task holds a shared resource at a time (typically with ownership + priority inheritance).
• (d) Semaphore: a signaling/counting primitive used to synchronize tasks or manage access to a set of resources (no ownership).

Q8. (4 marks)

• Priority inversion: a high-priority task is blocked waiting for a resource held by a low-priority task, while a medium-priority task preempts the low-priority one — effectively the high task waits on the medium task. (2)
• Priority inheritance: while a low-priority task holds a resource needed by a high-priority task, it temporarily inherits the high task's priority, so medium tasks cannot preempt it; once it releases the resource its original priority is restored. (2)

Q9. (3 marks)

• Purpose: a watchdog timer detects software hangs/lockups; if it is not reset within a timeout window, it triggers a system reset (or safe-state action). (2)
• Feeding/kicking: periodically resetting/reloading the watchdog counter (from healthy code) to prevent it timing out; a stuck program stops feeding it, so the watchdog resets the system. (1)

[
  {"claim": "PWM frequency = 16 kHz for 16 MHz clock, 1000 counts", "code": "f = 16e6/1000; result = (f == 16000)"},
  {"claim": "PWM period = 62.5 us", "code": "T = 1000*(1/16e6); result = abs(T - 62.5e-6) < 1e-12"},
  {"claim": "Duty cycle = 25% for CCR=250, ARR+1=1000", "code": "duty = 250/1000; result = (duty == 0.25)"},
  {"claim": "Nyquist minimum sample rate for 4 kHz is 8 kHz", "code": "fs = 2*4000; result = (fs == 8000)"},
  {"claim": "12-bit ADC resolution with 3.3V ref approx 0.806 mV", "code": "res = 3.3/(2**12); result = abs(res - 0.0008056640625) < 1e-9"}
]