Embedded Systems & Real-Time Software

Question 1

(a) Utilisation (2 marks): $U=\frac{1}{5}+\frac{2}{10}+\frac{5}{20}=0.2+0.2+0.25=0.65.$ LL bound (2): $U_{lub}(3)=3(2^{1/3}-1)=3(1.2599-1)=0.7798$. Since $U=0.65\le0.7798$, the LL sufficient test guarantees the set is schedulable under RM (1).

(b) RTA for $\tau_3$; $hp(3)=\{\tau_1,\tau_2\}$ (1 mark for setup). Start $R^{(0)}=C_3=5$. $R^{(1)}=5+\lceil5/5\rceil(1)+\lceil5/10\rceil(2)=5+1+2=8.$ $R^{(2)}=5+\lceil8/5\rceil(1)+\lceil8/10\rceil(2)=5+2+2=9.$ $R^{(3)}=5+\lceil9/5\rceil(1)+\lceil9/10\rceil(2)=5+2+2=9 \Rightarrow \text{converged}.$ $R_3=9\text{ ms}\le T_3=20\text{ ms}$ ⇒ schedulable. (6 marks for iterations + conclusion.)

(c)(i) Failure mode = priority inversion (1). Timeline: $\tau_1$ preempts and requests mutex held by $\tau_3$; without protocol, a medium task $\tau_2$ can preempt $\tau_3$ (which still holds the lock), so $\tau_1$ is blocked for an unbounded time — as long as $\tau_2$-class work keeps running (2 for explanation + sketch). Worst uncontrolled delay ≫ $B$. (ii) With priority inheritance the blocking is bounded by one critical section $B=3$ ms. RTA of $\tau_1$ (highest priority, $hp(1)=\varnothing$): $R_1=C_1+B=1+3=4\text{ ms}.$ $R_1=4\le T_1=5$ ⇒ still meets deadline. (4 marks: bounded blocking + computation + check.)

(d) DMA moves ADC samples to RAM without CPU per-sample ISR entry, so it removes the per-sample interrupt-latency contribution and the ISR execution time from every task's WCET, making timing deterministic and freeing the core for control. (4)

Question 2

(a) Nyquist $=f_s/2=500\text{ Hz}$ (1). Folding: $1300\text{ Hz}$ with $f_s=1000$: $1300-1000=300\text{ Hz}$ lies in band; general fold $|1300-1\cdot1000|=300\text{ Hz}$ (3). Alias appears at 300 Hz (1) — inside the 0–400 Hz band, corrupting the signal.

(b) To satisfy Nyquist for the highest present tone $1.3\text{ kHz}$: $f_s>2\times1300=2600\text{ Hz}$, so ≥ 2.6 kHz (2). If $f_s$ must stay 1 kHz, add an analog anti-alias low-pass filter with cutoff ≈400 Hz (below 500 Hz Nyquist) to attenuate the 1.3 kHz tone before the ADC (2).

(c) LSB $=3.3/2^{12}=3.3/4096=0.8057\text{ mV}$ (2). SQNR $=6.02(12)+1.76=72.24+1.76=74.0\text{ dB}$ (1). For LSB $<0.5\text{ mV}$: $3.3/2^N<0.5\times10^{-3}\Rightarrow 2^N>6600\Rightarrow N>\log_2 6600=12.69$, so $N=13$ bits (2).

(d) PWM freq $=f_{clk}/(\text{prescaler}\times\text{period})=80\times10^6/(1\times1024)=78125\text{ Hz}\approx78.1\text{ kHz}$ (4).

Question 3

(a) At 0x00000000: word0 = initial Main Stack Pointer (MSP); word1 = reset vector (address of Reset_Handler) (2). Code (4):

extern uint32_t _sidata,_sdata,_edata,_sbss,_ebss;
void Reset_Handler(void){
  uint32_t *src=&_sidata, *dst=&_sdata;
  while(dst<&_edata) *dst++=*src++;     // copy .data LMA->VMA
  for(dst=&_sbss; dst<&_ebss;) *dst++=0;// zero .bss
  main();
}

.bss holds zero-initialised variables; only the fact they are zero matters, so storing zeros in flash wastes ROM — the startup code writes zeros at runtime instead (2).

(b) Compare MSB→LSB. 0x2A5 = 101 0100 0101, 0x2A3 = 101 0100 0011. Bits identical until they differ: positions ...0101 vs 0011. At the bit where A sends 1 (recessive) and B sends 0 (dominant): wired-AND bus shows 0. A reads back 0 ≠ its 1, so A loses; B wins (2). Differing bit is the 3rd-from-LSB (value-4 bit): A=1, B=0 (2). Justification: dominant (0) overrides recessive (1); node reading a mismatch backs off non-destructively (2).

(c) Bit-wise majority (voter picks the value present in ≥2 channels): A=10110010, B=10100010, C=10110011. Per bit (MSB→LSB): 1,0,1,1/1/0,0,1,0 → checking bit3(from MSB) A=1,B=0,C=1→1; bit7 A=0,B=0,C=1→0; LSB A=0,B=0,C=1→0. Result 10110010 = A (2). Fail-safe: on channel loss the system moves to a defined safe state (e.g., outputs off/brakes). Fail-operational: the system continues correct operation using remaining healthy channels (2).

[
{"claim":"U=0.65 and LL bound(3) exceeds U","code":"U=Rational(1,5)+Rational(2,10)+Rational(5,20); lub=3*(2**Rational(1,3)-1); result=(U==Rational(13,20)) and (float(U)<=float(lub))"},
{"claim":"RTA R3 converges to 9","code":"import math\nC={1:1,2:2,3:5};T={1:5,2:10,3:20}\nR=C[3]\nfor _ in range(10):\n    nR=C[3]+math.ceil(R/T[1])*C[1]+math.ceil(R/T[2])*C[2]\n    if nR==R: break\n    R=nR\nresult=(R==9 and R<=T[3])"},
{"claim":"R1 with inheritance blocking =4 <=5","code":"R1=1+3; result=(R1==4 and R1<=5)"},
{"claim":"1300Hz aliases to 300Hz at fs=1000","code":"fs=1000;f=1300;a=abs(f-round(f/fs)*fs);result=(a==300)"},
{"claim":"12-bit LSB and 13 bits needed for <0.5mV","code":"lsb=Rational(33,10)/4096;need=13;result=(abs(float(lsb)-0.0008056640625)<1e-9) and (3.3/2**13<0.5e-3) and (3.3/2**12>=0.5e-3)"},
{"claim":"PWM freq =78125 Hz","code":"result=(80000000/(1*1024)==78125)"},
{"claim":"CAN: B(0x2A3) wins over A(0x2A5)","code":"A=0x2A5;B=0x2A3;win=B if B<A else A;result=(win==0x2A3)"}
]