Interrupts — ISR design, NVIC priority, interrupt latency

5.5.7 · Coding › Embedded Systems & Real-Time Software

WHY interrupts exist

HOW the hardware handshake works (Cortex-M)

Kyunki caller-saved registers hardware se stack hote hain, tumhara ISR ek normal C function ho sakta hai — compiler callee-saved ( $R 4$ – $R 11$ ) registers handle karta hai agar tum unhe use karo.

Figure — Interrupts — ISR design, NVIC priority, interrupt latency

NVIC priority — DERIVED from first principles

Interrupt latency — DERIVED

ISR design rules (jo 80/20 matter karta hai)

Flashcards

Hardware level pe ISR kya karta hai?

Hardware current context save karta hai (auto-stacks 8 registers) aur vector table ke zariye ISR address pe jump karta hai, phir return pe unstack karta hai.

Cortex-M pe, lower ya higher priority number jeetega?

Lower number = higher priority (0 sabse urgent hai).

Preemption priority aur sub-priority mein fark?

Preemption priority decide karta hai kaun ek running ISR ko interrupt kar sakta hai; sub-priority sirf simultaneously-pending equal-preemption IRQs ke beech ties break karta hai aur kabhi preemption nahi karta.

Agar chip N priority bits implement kare aur p bits preemption ko assign kare, toh kitne preempt aur sub levels honge?

2^p preemption levels aur 2^(N-p) sub-priority levels.

Interrupt latency define karo.

Event ke interrupt assert karne se lekar ISR ki pehli instruction execute hone tak ka time.

Cortex-M3/M4 pe no wait states ke saath deterministic hardware latency kitni hai?

~12 cycles (stacking + vector fetch).

ISRs short kyun hone chahiye?

Jab ISR chal raha hota hai, equal/lower-priority interrupts block ho jaate hain, unki latency inflate hoti hai aur deadlines miss hone / data drop hone ka risk hota hai.

Tail-chaining kya optimize karta hai?

Back-to-back pending interrupts unstack+restack skip karte hain (~6 cycles instead of ~24).

Shared ISR/main variables volatile kyun hone chahiye?

Taaki compiler ko force kiya ja sake ki woh unhe har baar memory se re-read kare, register mein stale value cache karne ki jagah.

Cortex-M interrupt entry pe auto-stack kye 8 registers karte hain?

R0–R3, R12, LR, PC, xPSR.

Do cheezein batao jo tumhe ISR ke andar KABHI nahi karni chahiye.

Blocking/long operations aur non-reentrant functions call karna (e.g. malloc, printf).

Software masking se latency kaunsa term badhata hai?

t_blocked — woh time jab interrupts disabled the (critical section / BASEPRI / __disable_irq).

Recall Feynman: ek 12-saal ke bachchon ko samjhao

Tum homework kar rahe ho (main program). Kitchen mein smoke alarm hai (interrupt). Jab woh beep kare, tumhe apna pencil exactly wahin chodna padta hai, smoke deal karna padta hai (ISR), phir pencil uthake wahi word likhna jaari rakhna padta hai. Alarm ka beep karna = hardware event. "Pencil ko exactly wahin chhodna" = CPU ka tumhare registers save karna. Kuch alarms zyada scary hote hain (fire > microwave timer) — yeh priority hai: fire alarm tumhe tab bhi interrupt karta hai jab tum already microwave answer kar rahe ho. Beep aur tumhare actually uthne ke beech ka time yeh latency hai — ise chota rakho aise kaam ke beech mein na phansa ke jo tum pause nahi kar sakte.

Connections

Real-Time Scheduling & Deadlines — latency directly bound karta hai ki deadlines meet hongi ya nahi.
Concurrency & Race Conditions — volatile + atomic access critical-section theory ko mirror karta hai.
ARM Cortex-M Architecture — vector table, stacking, BASEPRI register.
Polling vs Interrupt-driven I/O — efficiency tradeoff jo is poore topic ko motivate karta hai.
Ring Buffers / FIFO Queues — ISRs ke liye standard deferred-processing data structure.
Power Management & Sleep Modes — interrupts CPU ko low-power sleep se jagaate hain.