Level 1 — RecognitionEmbedded Systems & Real-Time Software

Embedded Systems & Real-Time Software

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Level 1 — Recognition Test

Time Limit: 20 minutes Total Marks: 30

Section A — Multiple Choice (1 mark each)

Choose the single best answer.

Q1. Which ARM Cortex-M core includes a hardware floating-point unit (FPU) and DSP instructions as standard, targeting signal-processing workloads?

(a) Cortex-M0
(b) Cortex-M3
(c) Cortex-M4
(d) Cortex-M0+

Q2. According to the Nyquist criterion, to reconstruct a signal with a maximum frequency component of 4 kHz, the minimum sampling rate must be:

(a) 2 kHz
(b) 4 kHz
(c) 8 kHz
(d) 16 kHz

Q3. In CAN bus arbitration, a lower numerical identifier value corresponds to:

(a) Lower priority
(b) Higher priority
(c) No effect on priority
(d) A dominant error frame

Q4. The resolution of a 12-bit ADC with a reference voltage of 3.3 V is closest to:

(a) 0.8 mV
(b) 1.6 mV
(c) 3.3 mV
(d) 12 mV

Q5. In FreeRTOS, the function used to create a new task is:

(a) xQueueCreate
(b) xTaskCreate
(c) vTaskDelay
(d) xSemaphoreTake

Q6. A watchdog timer that is NOT "fed" within its timeout period will typically:

(a) Raise a low-priority interrupt only
(b) Reset the microcontroller
(c) Enter sleep mode
(d) Increase CPU clock speed

Q7. Which standard governs airborne software for civil aviation?

(a) ISO 26262
(b) IEC 61508
(c) DO-178C
(d) MISRA C

Q8. In a linker script, uninitialized global/static variables are placed in the section:

(a) .text
(b) .data
(c) .bss
(d) .rodata

Q9. DMA is primarily used to:

(a) Increase CPU clock frequency
(b) Transfer data without CPU intervention
(c) Encrypt memory contents
(d) Provide floating-point acceleration

Q10. In Triple Modular Redundancy (TMR), the correct output is determined by:

(a) Averaging all three outputs
(b) Majority voting
(c) Selecting the fastest module
(d) Random selection

Section B — Matching (1 mark each, 6 marks)

Q11. Match each interface/bus (left) to its defining characteristic (right).

#	Interface		Characteristic
A	I2C	1	Differential twisted-pair, dominant/recessive bits, aerospace
B	SPI	2	Two wires (SDA/SCL), addressable master/slave
C	CAN	3	Full-duplex, separate MOSI/MISO/SCLK/SS lines
D	UART	4	Asynchronous, no shared clock, start/stop bits
E	SpaceWire	5	Command/response, dual redundant, military avionics
F	MIL-STD-1553	6	High-speed serial LVDS link for spacecraft

Section C — True / False with Justification (2 marks each: 1 for T/F, 1 for justification)

Q12. Priority inheritance solves the priority inversion problem by temporarily raising the priority of a low-priority task holding a shared resource. (True / False — justify)

Q13. A hard real-time deadline may be missed occasionally without any consequence to system correctness. (True / False — justify)

Q14. WCET (Worst Case Execution Time) analysis is only meaningful for the average-case runtime of a task. (True / False — justify)

Q15. A Memory Protection Unit (MPU) can be used to detect stack overflow by marking a guard region as inaccessible. (True / False — justify)

Q16. In SIL (Software-in-the-Loop) testing, the real target hardware runs against a simulated plant model. (True / False — justify)

Q17. MISRA C is a set of guidelines to make C code safer and more portable in critical systems. (True / False — justify)

Q18. An enabled GPIO pin-change interrupt requires the CPU to continuously poll the pin in a loop to detect changes. (True / False — justify)

End of paper

Answer keyMark scheme & solutions

Section A — MCQ (1 mark each)

Q1. (c) Cortex-M4. The M4 adds a single-precision FPU (optional) and DSP/SIMD instructions over the M3; M0/M0+ are minimal integer cores. (1)

Q2. (c) 8 kHz. Nyquist: $f_s \ge 2 f_{max} = 2 \times 4\,\text{kHz} = 8\,\text{kHz}$ . (1)

Q3. (b) Higher priority. CAN uses dominant (0) / recessive (1) bit arbitration; the frame with the lower ID wins the bus (more dominant bits early), so lower ID = higher priority. (1)

Q4. (a) 0.8 mV. $V_{LSB} = \dfrac{V_{ref}}{2^n} = \dfrac{3.3}{4096} \approx 8.06\times10^{-4}\,\text{V} = 0.806\,\text{mV}$ . (1)

Q5. (b) xTaskCreate. This is the FreeRTOS API to create a task; the others create queues, delay, or take semaphores. (1)

Q6. (b) Reset the microcontroller. A watchdog that times out assumes the software has hung and triggers a system reset to recover. (1)

Q7. (c) DO-178C. DO-178C is the airborne software standard; ISO 26262 = automotive, IEC 61508 = generic functional safety, MISRA C = coding guideline. (1)

Q8. (c) .bss. Uninitialized (zero-initialized) statics go in .bss, which occupies no ROM space and is zeroed at startup. (1)

Q9. (b) Transfer data without CPU intervention. DMA moves data between memory/peripherals independently, freeing the CPU. (1)

Q10. (b) Majority voting. TMR uses 2-of-3 majority voting to mask a single faulty module. (1)

Section B — Matching (1 mark each)

Q11.

A–2 (I2C: two-wire SDA/SCL, addressable)
B–3 (SPI: full-duplex MOSI/MISO/SCLK/SS)
C–1 (CAN: differential, dominant/recessive)
D–4 (UART: asynchronous, start/stop bits)
E–6 (SpaceWire: high-speed LVDS serial for spacecraft)
F–5 (MIL-STD-1553: command/response, dual-redundant avionics)

(6 marks; 1 each)

Section C — True/False with Justification (2 marks each)

Q12. TRUE. (1) Justification: Under priority inheritance, when a high-priority task blocks on a resource held by a low-priority task, the low-priority task is temporarily boosted to the blocked task's priority so it finishes and releases the resource quickly, avoiding unbounded blocking by medium-priority tasks. (1)

Q13. FALSE. (1) Justification: A hard deadline miss is a system failure; missing it can be catastrophic. Occasional misses that are tolerable describe a soft deadline. (1)

Q14. FALSE. (1) Justification: WCET is by definition the worst-case (maximum) execution time, not the average; it is used to guarantee schedulability under all conditions. (1)

Q15. TRUE. (1) Justification: Placing a no-access guard region just past the stack limit causes an MPU fault the moment the stack grows into it, catching overflow before memory corruption. (1)

Q16. FALSE. (1) Justification: SIL runs all software on a host against a simulated environment (no target hardware). Running the real target hardware against a simulated plant is HIL. (1)

Q17. TRUE. (1) Justification: MISRA C provides coding rules/guidelines restricting error-prone C constructs to improve safety, reliability, and portability in critical embedded software. (1)

Q18. FALSE. (1) Justification: A pin-change interrupt is asynchronous — a hardware edge/level triggers the ISR via the NVIC/EXTI without CPU polling; that is the advantage over polling. (1)

[
  {"claim":"Nyquist rate for 4 kHz max frequency is 8 kHz","code":"fmax=4000; fs=2*fmax; result = (fs==8000)"},
  {"claim":"12-bit ADC with 3.3V ref has LSB ~0.806 mV","code":"vlsb=Rational(33,10)/2**12; result = abs(float(vlsb)-0.000806)<1e-5"},
  {"claim":"TMR majority voting output for (1,0,1) is 1","code":"votes=[1,0,1]; out=1 if sum(votes)>=2 else 0; result = (out==1)"},
  {"claim":"bss holds zero-initialized data, occupies no ROM","code":"rom_needed_for_bss=0; result = (rom_needed_for_bss==0)"}
]