Intuition The one core ideaA CPU is a machine that does one tiny step at a time, over and over, incredibly fast — and ARM's whole personality is: keep each step as simple and same-sized as possible so the machine never gets confused about what's next. Everything in the parent note (registers, pipelines, load/store, conditional execution) is just a consequence of that single obsession with simplicity and predictability .
This page assumes you know nothing . We build every word the parent note used, in the order that lets each one lean on the previous. Read top to bottom.
Definition CPU and ARM — the two words in the title
A CPU (Central Processing Unit) is the "brain" chip that fetches commands and does the work — the piece that actually computes.
ARM (Advanced RISC Machine) is a family of designs (a blueprint) for how such a CPU should be built, famous for being simple and power-thrifty. Throughout this page "CPU" means the generic brain; "ARM" means the specific style of brain we're studying.
A bit is a single choice between two states — we write them 0 1
Every number, letter, and instruction inside a CPU is only a pattern of these on/off wires. If you can't picture a bit, nothing else has ground to stand on.
Info Figure 1 — bit → byte → wordWhat it shows: one green cell is a single bit ; eight cells side by side make a byte ; four coloured bytes stacked make one 32-bit word . Why it matters: this is the size ladder every later idea stands on — an ARM instruction and an ARM register are each exactly one word (32 bits) wide.
Definition Bit, byte, word
Bit = 1 wire (0 or 1).Byte = 8 bits grouped together, e.g. 01101001.Word (on 32-bit ARM) = 32 bits = 4 bytes. This is the "natural chunk size" the CPU likes to move and compute on.
The parent note says instructions are "32 bits" — that just means one instruction is exactly one word wide : 32 on/off wires.
Definition Binary (base-2) numberA row of bits is read like an odometer where each column is worth twice the column to its right: … , 8 , 4 , 2 , 1 1
Intuition Why binary and not decimalA wire is easily "off or on" (2 states) but hard to make "exactly 7 out of 10 voltages". Two clean states are reliable — which is exactly why aerospace, where a glitch is unacceptable, loves this simplicity. Numbers are just built out of these reliable 2-state wires.
With 32 bits you can represent 2 32 ≈ 4.29
The reading above ("add the columns") only ever gives non-negative numbers — it's the unsigned reading. But real programs need negatives too. The exact same 32 wires must somehow also mean − 1 − 5 top bit .
Definition Two's-complement (how negatives are stored)In two's-complement , the top (leftmost) bit's column is worth its usual size but negative . For an 8-bit byte that top column is − 128 + 128 value = − b 7 ⋅ 128 + b 6 ⋅ 64 + ⋯ + b 0 ⋅ 1 10000000 = − 128 11111111 = − 128 + 127 = − 1 1 which is exactly what the N flag reports.
Worked example Same bits, two meaningsThe byte 11111111:
read unsigned : 128 + 64 + ⋯ + 1 = 255
read two's-complement (signed) : − 1
Nothing on the wires changes — only how we choose to read the top bit . That choice is why we need two different overflow warnings : C catches unsigned overflow, V catches signed overflow (see §6).
A register is a small, ultra-fast storage box built from bits, living inside the CPU , that holds exactly one word (32 bits on 32-bit ARM). Think of it as a labelled slot on the chef's counter — right where the math happens.
The register file is the collection of all these boxes together. ARM's 32-bit core has 16 of them, named R 0 R 15
Info Figure 2 — registers (counter) vs memory (warehouse)What it shows: on the left, the 16 fast on-chip registers (with SP, LR, PC in coral); in the middle, the ALU which is wired only to those registers; on the right, slow external memory addressed as addr 000, 001, …. The coral LDR arrow copies warehouse → counter, the lavender STR arrow copies counter → warehouse. Why it matters: it is the whole load/store rule in one picture — arithmetic happens only on the counter, never in the warehouse.
Intuition Why registers exist at allReaching into main memory is slow (many steps away). A register is right there next to the arithmetic unit, so reading/writing it costs almost nothing. This is exactly why the parent note says "more registers ⇒ fewer slow memory trips". See Registers and Register File .
The notation R 0 … R 15 names for the 16 boxes — no math, just labels. Three of them have nicknames because the CPU uses them for special jobs:
R 13 = SP (Stack Pointer) — remembers the top of the "scratchpad stack".R 14 = LR (Link Register) — remembers where to return after a function call.R 15 = PC (Program Counter) — holds the address of the next instruction to fetch . This one is the CPU's "you are here" bookmark.
Common mistake "If I readR 15 Why it feels right: PC is "you are here", so surely it points at the instruction doing the reading.
The fix: On classic ARM, because the pipeline has already fetched instructions ahead, reading PC as an operand gives current instruction address + 8 (two 4-byte instructions further on, in ARM state). This is a real quirk you must account for when a program uses PC in arithmetic — a direct side-effect of the pipeline you'll meet in §7.
Memory (RAM) is a huge array of byte-boxes outside the fast register area. It's the fridge/warehouse : lots of room, but slower to reach than the counter.
Every box in memory has a number that names its location — its address . When we write [R1] in ARM, the brackets mean "the memory box whose address is the number sitting in R 1 . So R 1 [R1] is the thing at that address.
Intuition Why the distinction mattersThe whole "load/store" idea in the parent note only makes sense once you see: registers = counter (fast, few), memory = warehouse (slow, huge) . The gap in speed between them is why chips add caches — see Memory Hierarchy and Cache .
An instruction is one 32-bit word whose bit-pattern the CPU reads as a command , like "add these two boxes". It has two parts:
opcode = what to do (ADD, LDR, STR...),operands = which boxes to do it with (R 4 R 5
ADD R6, R4, R5
Opcode ADD = "add". Operands say: put ( R 4 + R 5 ) R 6 one 32-bit word .
Intuition Why fixed 32-bit width is a big dealBecause every instruction is the same size , the CPU knows the next one starts exactly 4 bytes later — without decoding the current one . That predictability is the seed of the whole RISC philosophy (see RISC vs CISC ) and the smaller 16-bit variant Thumb Instruction Set .
Definition ALU (Arithmetic Logic Unit)The ALU is the circuit inside the CPU that performs arithmetic (+ −
Intuition Why "the ALU only touches registers" (load/store)The ALU is wired directly to the register file, not to slow memory. So to compute on a memory value you must first LDR (LoaD Register — copy warehouse → counter), compute, then STR (STore Register — copy counter → warehouse). This is the load/store architecture the parent note builds on.
Definition Status flags (N, Z, C, V)After an operation, the CPU jots down four yes/no facts about the result:
N (Negative) — result's top bit is 1, i.e. negative under the two's-complement reading from §1.Z (Zero) — result was exactly zero.C (Carry) — an add overflowed past the top bit (or a borrow happened) — this is the unsigned overflow warning.V (oVerflow) — the signed (two's-complement) math wrapped around wrongly, e.g. adding two positives and getting a negative.
Definition CPSR (Current Program Status Register)The CPSR is a special register that stores these four flags (plus a few mode bits). It's the CPU's little pad of sticky notes recording "how did the last operation go?".
Intuition Why flags exist — they power conditional executionThe parent note's star feature ADDEQ ("add only if equal") works by reading the Z flag . A CMP R0, R1 subtracts and sets Z=1 if they were equal; then ADDEQ looks at Z. No flags → no way to say "only if". See how this dodges branches in Instruction Pipelining .
Info Figure 3 — flags drive conditional executionWhat it shows: CMP R0, R1 subtracts and writes the four flags into the CPSR (here R0==R1 sets the coral Z flag to 1); then ADDEQ reads that Z flag and only runs when Z=1. Why it matters: it's the mechanism behind branch-free ifs — because no jump happens, the pipeline is never flushed, so timing stays predictable (crucial for aerospace).
Definition Clock and clock cycleA clock is a wire that ticks on/off billions of times a second. One tick-to-tick interval is a clock cycle , duration τ
τ n k S
τ one cycle (e.g. 1 ns n how many instructions we run,k how many stages each instruction is split into,S speedup : how many times faster the pipelined CPU finishes the same job than a non-pipelined one. S = T pipe T serial S = 2
Definition Pipeline stageA stage is one station on the CPU's assembly line. The classic five: Fetch → Decode → Execute → Memory → Write-back . While one instruction is in "Execute", the next is in "Decode", the one after in "Fetch" — like cars on a factory line.
That is exactly the setup behind the parent's formula S = k + n − 1 nk S Real-Time Systems and WCET . (And this same "fetch ahead" behaviour is why reading PC gives +8, as noted in §2.)
Definition Performance-per-wattPerformance-per-watt = useful work done ÷ electrical power burned . Here "useful work" is a concrete, countable metric: the number of instructions completed per second (often measured in instructions per second or floating-point operations per second ). A watt is the unit of power (energy used per second). So the metric is literally instructions-per-second ÷ watts = instructions completed per joule of energy . On a battery or a spacecraft, you can't just crank the clock — you must maximise this ratio. Simple RISC hardware wins here; see Power and Performance-per-Watt .
This feeds directly into the parent ARM intro .
Test yourself — cover the right side and answer first.
What does CPU stand for and what is it? Central Processing Unit — the "brain" chip that fetches and executes commands.
What does ARM stand for? Advanced RISC Machine — a family of simple, power-efficient CPU designs.
What is a bit, physically? One wire that is either low voltage (0) or high voltage (1) — a single yes/no.
How many bits in a 32-bit ARM word? 32 bits = 4 bytes.
Read the binary 1011 as a decimal number. 8 + 2 + 1 = 11
Read the byte 11111111 both unsigned and as two's-complement. Unsigned = 255; two's-complement (signed) = − 1
In two's-complement, what is special about the top bit? Its column counts as negative (e.g. − 128
What is a register and where does it live? A tiny fast box holding one word, living inside the CPU right next to the ALU.
How many general-purpose registers on 32-bit ARM, and what are they called? 16, named R 0 R 15
Which registers are SP, LR, PC? R 13 R 14 R 15
When you read PC (R15) as an operand on classic ARM, what value do you get? Current instruction address + 8, because the pipeline has already fetched ahead.
In LDR R4, [R1], what does [R1] mean? The memory box whose address is the number stored in R 1
What can the ALU operate on directly — memory or registers? Registers only (that's the load/store rule).
What are the four flags and where are they stored? N, Z, C, V — stored in the CPSR.
Which flag catches unsigned overflow and which catches signed overflow? C catches unsigned overflow; V catches signed (two's-complement) overflow.
What sets the Z flag to 1? An operation whose result was exactly zero (e.g. CMP R0,R1 when equal).
In the pipeline formula, what do n k τ S n k τ S
Name the five classic pipeline stages in order. Fetch, Decode, Execute, Memory, Write-back.
Give a concrete metric for performance-per-watt. Instructions completed per second ÷ watts = instructions completed per joule of energy.
