Visual walkthrough — ARM architecture intro — used in embedded - aerospace

Prerequisites we lean on: Instruction Pipelining, RISC vs CISC, and the parent ARM intro.

Step 1 — What is one instruction actually made of?

WHAT. Before we can time anything, we must know what we are timing. Every instruction the CPU runs is chopped into a fixed list of small jobs called stages. In the classic ARM core there are five:

$\underset{\text{Fetch}}{\underbrace{F}}\to \underset{\text{Decode}}{\underbrace{D}}\to \underset{\text{Execute}}{\underbrace{E}}\to \underset{\text{Memory}}{\underbrace{M}}\to \underset{\text{Write-back}}{\underbrace{W}}$

• F (Fetch) — grab the instruction from memory.
• D (Decode) — figure out what it means, read registers.
• E (Execute) — do the ALU math.
• M (Memory) — talk to memory (only LDR/STR really use this — that's the load/store idea).
• W (Write-back) — write the result into a register.

WHY split it up at all? Because each little job needs different hardware (an adder, a decoder, a memory port). If we glue them into one giant step, most of that hardware sits idle most of the time. Splitting lets us keep every piece busy — which is the whole trick of Step 4.

PICTURE. One instruction = five coloured boxes in a row. Each box takes the same amount of time, which we call one tick of duration $\tau$ (Greek letter "tau", just a name for "how long one tick lasts, in nanoseconds").

Step 2 — The slow way: do everything one-at-a-time

WHAT. First measure the naive machine that has no pipeline: it runs instruction A completely (all $k$ stages) before even starting instruction B.

WHY start here? You cannot say something is "5× faster" until you have the slow thing to compare against. This is our baseline.

PICTURE. Look at the figure: instruction A fills 5 ticks, then B fills the next 5, then C. Notice the huge waste — while A is in Execute, the Fetch hardware is doing nothing.

Each instruction costs $k$ ticks of $\tau$, and there are $n$ of them, so:

$T_{\text{serial}}=\underset{\text{how many}}{\underbrace{n}}\times \underset{\text{stages each}}{\underbrace{k}}\times \underset{\text{time per stage}}{\underbrace{\tau }}$

For $n=1000,k=5,\tau =1\text{ns}$: $T_{\text{serial}}=1000\times 5\times 1=5000\text{ns}$.

Step 3 — The key observation: stages are different workers

WHAT. Stare at the wasted white space in Step 2's picture. The Fetch worker is free the instant instruction A moves on to Decode. So why not let it fetch instruction B right now?

WHY it's allowed. Because the five stages use separate hardware. Fetching B does not disturb A's decode — they touch different circuits. This only works cleanly because ARM instructions are fixed length: the Fetch unit always knows where the next instruction starts without waiting for anyone. (This is the payoff of RISC's fixed-width instructions.)

PICTURE. We slide instruction B one tick to the right of A, so B's Fetch lines up under A's Decode. No two instructions ever sit in the same stage at the same tick — that's the rule that keeps it legal.

Step 4 — Draw the full pipeline and count the ticks

WHAT. Extend Step 3 to all $n$ instructions: each one starts exactly one tick after the one before it. This staircase pattern is the pipeline.

WHY it gives a formula. The finished instructions come out of the last stage at a steady beat, and we can literally count the ticks off the diagram.

PICTURE. The diagonal "staircase". Two regions matter:

• The fill (magenta): the first instruction still has to walk through all $k$ stages before anything finishes. That costs $k$ ticks.
• The steady stream (orange): after the pipe is full, one instruction pops out every single tick. The remaining $n-1$ instructions each add just one more tick.

Add the two regions:

$T_{\text{pipe}}=\underset{\text{fill the pipe once}}{\underbrace{k}}+\underset{\text{one extra tick per later instruction}}{\underbrace{(n-1)}}\text{ticks}=(k+(n-1))\tau$

For $n=1000,k=5,\tau =1\text{ns}$: $T_{\text{pipe}}=(5+999)\times 1=1004\text{ns}$.

Compare: $5000\text{ns}$ vs $1004\text{ns}$. Almost five times faster, for the same hardware doing the same work — just never idle.

Step 5 — Turn the counts into the speedup formula

WHAT. "Speedup" $S$ is simply the honest ratio old time ÷ new time.

WHY a ratio? A ratio cancels the units ($\tau$ disappears) and answers the plain-English question: "how many times faster?"

$S=\frac{T_{\text{serial}}}{T_{\text{pipe}}}=\frac{nk\tau }{(k+n-1)\tau }=\frac{nk}{k+n-1}$

Term by term:

• $nk$ on top = total work measured in ticks (Step 2).
• $k+n-1$ on bottom = fill + stream (Step 4).
• The $\tau$'s cancel — speedup does not care how fast a tick is, only about the overlap.

Plug in the numbers: $S=\frac{1000\times 5}{5+1000-1}=\frac{5000}{1004}\approx 4.98$.

Step 6 — Push $n$ to infinity: where does the $k$ come from?

WHAT. Ask: what happens if we run lots and lots of instructions ($n$ grows huge)?

WHY the limit tool? A limit answers "what value does this ratio settle toward as $n$ keeps growing?" — exactly the right question, because a real program runs millions of instructions, so the tiny fixed fill cost stops mattering. We use a limit, not just "plug in a big number", because it gives the exact ceiling the speedup can never beat.

Divide top and bottom by $n$ (a legal move — same value, just rewritten):

$S=\frac{nk}{k+n-1}=\frac{k}{\frac{k}{n}+1-\frac{1}{n}}$

As $n\to \infty$, the terms $\frac{k}{n}$ and $\frac{1}{n}$ both shrink toward $0$:

$S\stackrel{n\to \infty }{\to }\frac{k}{0+1-0}=k$

PICTURE. The speedup curve climbs steeply for small $n$, then flattens and hugs the dashed ceiling line $S=k$. It approaches but never reaches $k$ — because the $k$-tick fill is a debt you always pay once.

Step 7 — The edge cases (so you never hit a surprise)

Every honest derivation must survive its extremes. Check the boundaries.

Case $n=1$ (one lonely instruction). Plug in: $S=\frac{1\cdot k}{k+1-1}=\frac{k}{k}=1$ No speedup at all — and that's correct: with a single instruction there is nothing to overlap. The pipeline only helps when instructions can share the assembly line.

Case $k=1$ (only one stage). Then $S=\frac{n\cdot 1}{1+n-1}=\frac{n}{n}=1$. A one-stage "pipeline" isn't a pipeline; nothing to overlap, so speedup 1. Reassuring.

Case: a branch mispredict (the real-world spoiler). Our staircase assumed instructions flow in a known order. A wrong-way branch means the half-built instructions in the pipe were the wrong ones — we flush them and pay the $k$-tick fill again. This is exactly why aerospace cores keep $k$ small and why ARM offers conditional execution to dodge branches entirely.

The one-picture summary

This single figure stacks the whole story: the serial bars (top, wasteful), the pipelined staircase (middle, overlapping), and the speedup curve flattening toward $k$ (right). Trace one instruction diagonally and you see the $k+(n-1)$ count; read the ratio and you see the $S\to k$ ceiling.

Active recall