Level 1 — RecognitionComputer Architecture (Deep)

Computer Architecture (Deep)

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Time limit: 20 minutes Total marks: 30 Instructions: Answer all questions. For True/False items, a correct justification is required for full marks.

Section A — Multiple Choice (1 mark each)

Q1. In the classic Von Neumann architecture, the "bottleneck" refers to:

(a) The ALU being slower than the control unit
(b) The single shared bus/path between CPU and memory limiting throughput
(c) The lack of registers
(d) Cache misses forcing disk access

Q2. Harvard architecture differs from Von Neumann primarily because it:

(a) Has no ALU
(b) Uses separate memories/buses for instructions and data
(c) Cannot execute programs
(d) Requires virtual memory

Q3. Which is a defining characteristic of RISC compared to CISC?

(a) Variable-length, complex instructions
(b) Fixed-length, simple instructions with load/store architecture
(c) Direct memory-to-memory arithmetic on all operations
(d) No pipelining possible

Q4. The ARM register that holds the return address for a subroutine call is:

(a) PC
(b) SP
(c) LR
(d) CPSR

Q5. In a MIPS R-type instruction, which field is present that a J-type lacks?

(a) opcode
(b) a 26-bit jump target
(c) rs, rt, rd register fields
(d) an immediate constant

Q6. A cache with a block/line size of 64 bytes uses how many bits for the byte offset?

(a) 4
(b) 5
(c) 6
(d) 8

Q7. Which write policy updates only the cache on a write and marks the line dirty for later memory update?

(a) Write-through
(b) Write-back
(c) Write-allocate
(d) No-write-allocate

Q8. In the MESI protocol, the state meaning "this cache holds the only copy and it is unmodified" is:

(a) Modified
(b) Exclusive
(c) Shared
(d) Invalid

Q9. A TLB is best described as:

(a) A cache of virtual-to-physical address translations
(b) A branch predictor table
(c) The main page table in RAM
(d) A write buffer

Q10. The Optimal page replacement algorithm evicts the page that:

(a) Was loaded first
(b) Has been used least often
(c) Will not be used for the longest time in the future
(d) Was least recently used

Q11. The addressing mode where the operand is contained directly in the instruction is:

(a) Register
(b) Immediate
(c) Indirect
(d) Indexed

Q12. A RAW (Read-After-Write) hazard is a type of:

(a) Structural hazard
(b) Data (true) dependency hazard
(c) Control hazard
(d) Coherence hazard

Section B — Matching (5 marks)

Q13. Match each 5-stage pipeline stage (left) to its function (right). (1 mark each)

Stage		Function
A. IF		1. Compute results / address in the ALU
B. ID		2. Read/write data cache
C. EX		3. Fetch instruction from memory
D. MEM		4. Write result to register file
E. WB		5. Decode & read registers

Section C — True / False with justification (2 marks each: 1 T/F, 1 justification)

Q14. In SIMT (GPU) execution, all threads in a warp always execute the same instruction, so branch divergence has no performance cost. — True or False? Justify.

Q15. Sequential consistency is a weaker (more relaxed) memory model than TSO (Total Store Order). — True or False? Justify.

Q16. Operand forwarding (bypassing) can eliminate every data hazard stall without ever needing a bubble. — True or False? Justify.

Q17. A 2-bit saturating branch predictor requires two consecutive mispredictions to flip its prediction direction. — True or False? Justify.

Section D — Short calculation (1 mark each)

Q18. A byte-addressable direct-mapped cache: 16 KB total, 32-byte lines. How many index bits are needed? (Show offset + index.)

Q19. Virtual memory with 4 KB pages, 32-bit virtual addresses. How many bits are the page offset, and how many entries are in a single-level page table?

Answer keyMark scheme & solutions

Section A (1 mark each)

Q1 — (b). The Von Neumann bottleneck is the single shared bus/path forcing instructions and data to travel serially between CPU and memory, capping throughput. (1)

Q2 — (b). Harvard uses physically separate instruction and data memories/buses, allowing simultaneous fetch of instruction and data. (1)

Q3 — (b). RISC = fixed-length simple instructions, load/store architecture (only load/store touch memory). (1)

Q4 — (c). LR (Link Register, R14 in ARM) stores the return address on BL. PC=program counter, SP=stack pointer, CPSR=status. (1)

Q5 — (c). R-type has rs, rt, rd (three register fields); J-type has a 26-bit target instead. (1)

Q6 — (c). $\log_2 64 = 6$ offset bits. (1)

Q7 — (b). Write-back writes only to cache, sets the dirty bit, and defers memory update until eviction. (1)

Q8 — (b). Exclusive = sole, clean copy. (1)

Q9 — (a). The TLB caches recent virtual→physical page translations to avoid full page-table walks. (1)

Q10 — (c). Optimal (Bélády) evicts the page whose next use is farthest in the future. (1)

Q11 — (b). Immediate addressing embeds the constant operand in the instruction. (1)

Q12 — (b). RAW is a true data dependency (instruction reads a value a prior instruction must first write). (1)

Section B

Q13 (5 marks, 1 each):

A–3 (IF: fetch instruction)
B–5 (ID: decode & read registers)
C–1 (EX: ALU compute)
D–2 (MEM: data-cache access)
E–4 (WB: write back to registers)

Q14 — FALSE. (1 T/F) Justification: within a warp threads run in lockstep, but on a divergent branch the hardware serializes the taken and not-taken paths (masking inactive threads), so divergence does cost performance. (1)

Q15 — FALSE. (1) Justification: Sequential consistency is the strongest model (all cores see one global program order). TSO relaxes store→load ordering (store buffers), so TSO is weaker, not SC. (1)

Q16 — FALSE. (1) Justification: Forwarding removes most ALU-to-ALU RAW stalls, but a load-use hazard still needs one bubble because the loaded value isn't available until after MEM. (1)

Q17 — TRUE. (1) Justification: In a 2-bit saturating counter the strong states resist change; it takes two consecutive wrong outcomes to cross from a strong prediction, through the weak state, to the opposite direction. (1)

Section D

Q18 (1 mark):

Offset: $\log_2 32 = 5$ bits.
Lines = $16384 / 32 = 512$ ⇒ index = $\log_2 512 = 9$ bits.
Answer: 9 index bits. (Award full mark for 9; note offset=5.)

Q19 (1 mark):

Page offset = $\log_2 4096 = 12$ bits.
Page number bits = $32 - 12 = 20$ ⇒ entries = $2^{20} = 1{,}048{,}576$ .
Answer: 12 offset bits, $2^{20}$ = 1,048,576 entries.

[
  {"claim":"Q6: 64-byte line needs 6 offset bits","code":"import math; result = (int(math.log2(64))==6)"},
  {"claim":"Q18: 16KB direct-mapped, 32B lines => 9 index bits, 5 offset bits","code":"total=16*1024; line=32; offset=int(math.log2(line)); lines=total//line; index=int(math.log2(lines)); result = (offset==5 and index==9)"},
  {"claim":"Q19: 4KB pages, 32-bit VA => 12 offset bits and 2**20 PTEs","code":"offset=int(math.log2(4096)); entries=2**(32-offset); result = (offset==12 and entries==1048576)"}
]