Computer Architecture (Deep)

Q1. (4 marks)

• Von Neumann uses a single shared memory and bus for both instructions and data; Harvard uses separate memories/buses for instructions and data. (1)
• Consequence: Harvard can fetch an instruction and access data simultaneously; Von Neumann cannot. (1)
• Von Neumann bottleneck: the single shared bus limits throughput because instruction fetch and data transfer must be serialized/multiplexed (1) — CPU speed outpaces the memory–CPU transfer rate, so the bus becomes the performance limiter. (1)

Q2. (4 marks) (1 each)

• Zero (Z): set when the ALU result is all zeros.
• Negative (N): set when the MSB (sign bit) of the result is 1.
• Carry (C): set when an unsigned add produces a carry-out (or borrow in subtraction).
• Overflow (V): set when a signed operation produces a result outside the representable range (sign of result wrong).

Q3. (3 marks) (any three, 1 each)

• Fixed-length, uniform instruction format (RISC) vs variable-length (CISC).
• Load/store architecture: only load/store touch memory (RISC) vs memory operands in many instructions (CISC).
• Simpler instructions, more registers, hardwired control (RISC) vs microcoded complex instructions (CISC).
• Fewer addressing modes in RISC.

Q4. (5 marks)

• Offset = $\log_2(32) = 5$ bits. (1)
• Number of blocks (lines) = $16\text{KB}/32 = 16384/32 = 512$ lines. (1)
• Index = $\log_2(512) = 9$ bits. (1)
• Tag = $32 - 9 - 5 = 18$ bits. (2)

Answer: offset = 5, index = 9, tag = 18.

Q5. (5 marks) FIFO, 3 frames. Reference: 7,0,1,2,0,3,0,4

Count of faults = 7. (marks: correct trace 3, correct count 2)

Q6. (5 marks) (1 each)

1. IF — Instruction Fetch: read instruction from memory using PC.
2. ID — Instruction Decode / register read: decode opcode, read registers.
3. EX — Execute: ALU operation / address calculation.
4. MEM — Memory access: load/store data.
5. WB — Write Back: write result to register file.

Q7. (4 marks)

• Structural hazard: two instructions need the same hardware resource at once. (1)
• Data hazard: an instruction depends on the result of a prior instruction not yet completed (RAW/WAR/WAW). (1)
• Control hazard: uncertainty from branches/jumps about the next instruction. (1)
• RAW mitigation other than stalling: forwarding/bypassing (route the ALU result directly to a dependent instruction). (1)

Q8. (4 marks) (1 each)

• Modified (M): line is dirty, present only in this cache; must write back.
• Exclusive (E): clean, present only in this cache, matches memory.
• Shared (S): clean, may be present in other caches.
• Invalid (I): line does not hold valid data.

Q9. (3 marks) (½ each, round up)

• (a) Immediate: operand is a constant in the instruction.
• (b) Register: operand is in a register.
• (c) Direct: instruction contains the memory address of the operand.
• (d) Indirect: instruction gives address of a location holding the operand's address.
• (e) Indexed: effective address = base register + index (offset).

Q10. (3 marks) States: 00 SNT, 01 WNT, 10 WT, 11 ST. Prediction = taken iff top bit = 1.

Mispredictions = 2. (trace 2, count 1)

[
  {"claim":"Q4 offset=5, index=9, tag=18 for 16KB direct-mapped, 32B block, 32-bit addr","code":"offset=Integer(32).bit_length()-1\nlines=(16*1024)//32\nindex=Integer(lines).bit_length()-1\ntag=32-index-offset\nresult=(offset==5 and index==9 and tag==18)"},
  {"claim":"Q5 FIFO 3 frames on 7,0,1,2,0,3,0,4 gives 7 faults","code":"refs=[7,0,1,2,0,3,0,4]\nframes=[]\norder=[]\nfaults=0\nfor r in refs:\n    if r not in frames:\n        faults+=1\n        if len(frames)<3:\n            frames.append(r); order.append(r)\n        else:\n            victim=order.pop(0); frames.remove(victim); frames.append(r); order.append(r)\nresult=(faults==7)"},
  {"claim":"Q10 2-bit predictor from 00, 4 consecutive takens gives 2 mispredictions","code":"state=0\nmis=0\nfor _ in range(4):\n    pred = state>>1\n    if pred!=1: mis+=1\n    state=min(state+1,3)\nresult=(mis==2 and state==3)"}
]