4.1.4
Intuition Is note ka 80/20ARM ek RISC (Reduced Instruction Set Computer) design philosophy hai. Pura point yahi hai: hardware ko simple, fast, aur power-efficient rakho, aur clever kaam compiler pe chhod do. Issi liye ARM phones, microcontrollers, aur aerospace flight computers mein dominate karta hai — jab battery pe ya radiation-hardened budget pe kaam karna ho, toh performance-per-watt raw clock speed se zyada important hota hai. Teen ideas master karo aur 80% samajh lo: (1) fixed-length, load/store instructions, (2) bahut saare registers, (3) conditional execution + ek simple, predictable pipeline.
ARM (originally Acorn RISC Machine , ab Advanced RISC Machines ) ek RISC instruction set architectures (ISAs) ki family hai. ARM ISA (software aur hardware ke beech ka contract) license karta hai — Apple, Qualcomm, aur ST jaisi companies actual silicon banati hain. Toh ARM ek design / specification hai, na ki (usually) ek chip vendor.
Definition ISA (Instruction Set Architecture)ISA woh set of instructions, registers, aur rules hain jo ek CPU programmer ko expose karta hai. Yeh abstraction boundary hai: software ISA ke liye likha jaata hai, hardware ISA ko implement karta hai. x86 aur ARM alag-alag ISAs hain.
Embedded/aerospace ke liye WHY matters:
Low power → batteries / harvested energy pe chalta hai.Deterministic timing → simple pipeline matlab aap worst-case execution time (WCET) predict kar sakte ho, jo real-time flight control ke liye zaroori hai.Small, cheap, scalable → tiny Cortex-M microcontrollers se lekar Cortex-A application processors tak.
Socho tumhe ek CPU design karna hai. Har instruction ko fetch, decode, execute karna padega. Do raaste hain:
CISC (e.g., x86): ek instruction bahut kuch kar sakti hai (e.g., "load from memory, multiply, store back" ek hi opcode mein). Instructions variable length ki hoti hain. Decoding complex hoti hai.RISC (ARM): har instruction ek simple kaam karti hai, saari instructions same length ki hoti hain, aur sirf khaas load/store instructions memory ko touch karti hain.
Intuition Pipeline ke liye fixed length kyun jeet jaata haiAgar har instruction exactly 32 bits ki hai (ya Thumb mein 16), toh CPU ko hamesha pata hota hai agli instruction kahan se shuru hogi — bina current wali ko decode kiye. Isse fetch stage trivial aur pipeline regular ban jaati hai. Regular pipeline ⇒ predictable timing ⇒ aerospace ke liye safe.
Definition Load/Store architectureARM mein, ALU sirf registers pe operate karta hai (aur immediates pe). Memory mein koi value use karni ho toh pehle use ek register mein LOAD karna padega; likhne ke liye use wapas STORE karna padega. Arithmetic kabhi bhi seedha memory se read nahi karta.
KYU? Memory access ki latency unpredictable hoti hai (cache miss!). "Memory se baat karo" (LDR/STR) aur "compute karo" (ADD/SUB) ko alag karke, har instruction ki ek zyada uniform, predictable cost hoti hai — phir se real-time guarantees mein madad karta hai.
Zyada registers KYU? Kyunki ALU memory ko touch nahi kar sakta, toh on-chip "scratch" slots ki achi khaasi zaroorat hoti hai. Zyada registers ⇒ kam slow memory trips ⇒ faster aur lower power.
Intuition Assembly-line analogyEk gaadi ko shuru se akhir tak banana slow hota hai. Use assembly line pe daalo: jab station 2 gaadi A ko paint kar raha hai, station 1 gaadi B shuru karta hai. Same idea: jab hum instruction A ko execute karte hain, hum B ko decode karte hain aur C ko fetch karte hain. Throughput roughly ek instruction per clock tak pahunch jaata hai, chahe har instruction abhi bhi kai stages leti ho.
Classic ARM stages: Fetch → Decode → Execute (aur 5-stage cores mein: Fetch, Decode, Execute, Memory, Write-back).
Definition Conditional executionARM ki almost har instruction ko predicated kiya ja sakta hai — woh sirf tab chalti hai jab flags ek condition se match karein (e.g., ADDEQ = sirf tab add karo jab Z=1 ho). Isse chote branches avoid hote hain.
Intuition Yeh pipeline ki madad kyun karta haiBranches pipelines ke dushman hain: agar aap galat andaza lagao ki branch kahan jaayegi, toh aapko half-built instructions ko flush karna padega. Predication ek chote if ko straight-line code mein badal deta hai — koi branch nahi, koi flush nahi, smoother timing. Aerospace deterministic code ke liye zabardast.
Worked example Example 1 — ARM meinC = A + B
C code: c = a + b; jahan a memory address R1 mein hai, b address R2 mein, result R3 mein.
LDR R4, [R1] ; load a into R4 — Kyun? ALU seedha memory read nahi kar sakta (load/store) LDR R5, [R2] ; load b into R5 — Kyun? same reason ADD R6, R4, R5 ; R6 = R4 + R5 — Kyun? arithmetic sirf registers pe STR R6, [R3] ; store result — Kyun? explicitly wapas likhna padega Lesson: 4 instructions, lekin har ek simple, fixed-length, predictable hai.
Worked example Example 2 — Pipeline speedup numbersn = 1000 k = 5 τ = 1 ns
Serial: T = 1000 ⋅ 5 ⋅ 1 = 5000 ns Kyun? koi overlap nahi.
Pipelined: T = ( 5 + 999 ) ⋅ 1 = 1004 ns Kyun? fill karne mein 5 cycles, phir 999 aur ek-per-cycle finish hote hain.
Speedup S = 5000/1004 ≈ 4.98 ≈ k ≈5 kyun? Bada n
Worked example Example 3 — Conditional execution ek branch se behtarCompute karo if (a==b) x = x+1;
CMP R0, R1 ; Z=1 set karta hai agar R0==R1 ADDEQ R2, R2, #1; sirf tab add karo jab equal ho — koi branch nahi liya Yeh step kyun? CMP flags update karta hai; ADDEQ unhe padhta hai. Koi jump nahi matlab pipeline kabhi flush nahi hoti → predictable cycle count.
Common mistake "ARM seedha memory pe arithmetic kar sakta hai jaiseADD [x], [y]."
Kyun sahi lagta hai: x86 mein aisa hota hai, aur efficient lagta hai — ek hi instruction!
Fix: ARM load/store hai — ALU ops sirf registers ko touch karte hain. Pehle LDR karna padega. Yeh separation jaanbujhkar hai, jo uniform instruction cost aur predictable timing deta hai.
Common mistake "Zyada pipeline stages matlab hamesha zyada speed."Kyun sahi lagta hai: Speedup → k k Fix: Har branch misprediction ab zyada cycles refill karne mein waste karta hai, aur per-stage register overhead badhti hai. Embedded/aerospace cores often pipelines short rakhte hain precisely peak throughput ke bajay predictability ke liye.
Common mistake "ARM apne chips khud banata hai."Kyun sahi lagta hai: "ARM processor" har jagah hai.
Fix: ARM mostly ISA/IP license karta hai; vendors (Apple, ST, NXP) silicon fab karte hain. ARM = blueprint, (usually) factory nahi.
Recall Feynman: ek 12-saal ke bache ko samjhaoCPU ko ek kitchen samjho. ARM ka rule hai: chefs (math wala part) sirf counter pe rakhe ingredients (registers) se hi cook kar sakte hain. Agar kuch fridge mein hai (memory), toh ek worker ko pehle use counter pe laana padega (LOAD), aur kaam ke baad wapas rakhna padega (STORE). Kyunki har recipe card same size ki hai aur ek chota sa step karta hai, kitchen ek smooth assembly line ki tarah chalta hai — fast aur bahut kam bijli use karke. Issi liye ARM tumhare phone mein hai aur spaceships mein bhi, jahan power bachana aur timing ke baare mein kabhi confuse na hona sach mein important hai.
"A R M = All Registers Mostly" — Saare ops Registers use karte hain, Memory sirf load/store se.
Flags N Z C V ke liye → "Never Zap Cute Vultures."
RISC ka full form kya hai aur uska core idea kya hai? Reduced Instruction Set Computer — simple, fixed-length instructions; hardware simple rehta hai, clever kaam compiler karta hai.
Load/store architecture mein, kya ALU seedha memory se read kar sakta hai? Nahi. Pehle LDR se value register mein laani padti hai; arithmetic sirf registers/immediates pe kaam karta hai.
ARM ke kaunse registers special hain aur woh kya hain? R13=SP (stack pointer), R14=LR (link register), R15=PC (program counter).
CPSR mein kaunse chaar flags hote hain? N (Negative), Z (Zero), C (Carry), V (oVerflow).
n instructions, k stages, cycle τ ke liye pipeline time derive karo. T = (k + n − 1)·τ; speedup S = nk/(k+n−1) → k as n→∞.
Conditional execution pipelines ke liye achha kyun hai? Yeh chote branches ko predicated straight-line code se replace karta hai, branch mispredict flushes avoid hote hain → predictable timing.
Kya ARM zyataar ARM chips manufacture karta hai? Nahi — ARM ISA/IP license karta hai; vendors silicon fabricate karte hain.
ARM aerospace/embedded mein kyun preferred hai? Low power (performance-per-watt), simple predictable pipeline (deterministic WCET), aur scalable cores.
ARM ka fetch stage simple kya banata hai? Fixed-length instructions (32-bit, ya 16-bit Thumb) — CPU ko hamesha pata hota hai agli instruction kahan se shuru hoti hai.
ISA - software/hardware contract
Apple Qualcomm ST silicon
Fixed-length instructions
Load/Store only touches memory
