5.1.3Instruction Set Architecture (ISA)

Addressing modes

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WHY do addressing modes exist?

Three pressures shape them:

  • WHY (flexibility): arrays need index, pointers need indirection, loops need auto-increment.
  • WHY (compactness): small constants and nearby data shouldn't cost a full 32-bit address.
  • WHY (speed): register operands are fastest; smart modes reduce instruction count.

WHAT is being computed: the Effective Address


HOW each mode works (derive the EA rule from scratch)

Let the instruction contain a field AA (an address or displacement) and possibly a register name RR. Let M[x]M[x] mean "contents of memory at xx" and (R)(R) mean "contents of register RR".

WHY each rule looks like it does:

  • Immediate — the constant is baked into the instruction, so no address is needed. Fastest, but the value is fixed at compile time and limited by field width.
  • Direct — the address bits are the address. Simple, but AA must be wide enough to name any location.
  • IndirectAA names a pointer cell; the CPU reads it to get the real address. Enables following linked structures, but costs an extra memory read.
  • Displacement (A+(R)A+(R)) — the workhorse. RR holds a base (start of array/struct/stack frame), AA is a small offset. This is why array A[i] and struct fields are cheap.
  • PC-relative — makes code position-independent: a branch stores how far to jump, not an absolute target, so the program runs correctly wherever it's loaded.
  • Auto inc/dec — bakes pointer-stepping into the access, perfect for stacks (push/pop) and streaming through arrays.
Figure — Addressing modes

Worked examples

Assume memory and registers:

Address Contents Register Contents
100 500 R1 400
400 700 R2 3
500 800 PC 200
403 900

Common mistakes (steel-manned)


The 80/20 core


Flashcards

What does an addressing mode determine?
The rule for computing where the operand is (its effective address) from the instruction bits and registers.
Define effective address (EA).
The final memory address of the operand after the addressing-mode rule is applied.
Immediate mode: how many memory accesses for the operand?
Zero — the operand value is stored inside the instruction itself.
EA rule for direct mode?
EA = A (the address field is the address).
EA rule for indirect mode and its cost?
EA = M[A]; needs 2 memory accesses (read pointer, then read operand).
Difference between register-indirect and memory-indirect?
Register-indirect: EA=(R), 1 access. Memory-indirect: EA=M[A], 2 accesses.
EA rule for displacement/based mode?
EA = A + (R): base register plus a constant offset.
Why is PC-relative mode used for branches?
It stores a distance/offset (EA = PC + A), making code position-independent/relocatable.
Which mode is ideal for stack push/pop and array streaming?
Auto-increment / auto-decrement.
Which two modes cover ~80% of real instructions?
Register mode and displacement (base+offset) mode.
In LOAD 3(R1) with (R1)=400, what is EA?
403 (EA = 3 + 400).
Trade-off of adding many complex addressing modes?
Fewer instructions but more complex decode/longer critical path (CISC vs RISC trade-off).

Recall Feynman: explain to a 12-year-old

Imagine a treasure map. Sometimes the map says "the gold is RIGHT HERE" (immediate — the answer is written on the map). Sometimes it says "gold is buried at spot #100" (direct — go dig at 100). Sometimes spot #100 has another note saying "actually it's at spot #500" (indirect — one extra trip). Sometimes it says "start at the big tree (in your pocket = a register) and walk 3 steps" (displacement). And "PC-relative" is like "from where you're standing, go 6 steps forward" — so the treasure hunt works no matter where the park sets up the game. Every kind of map is just a different way of saying where to finally dig.


Connections

Concept Map

mode bits select

computes

contents M of EA

no memory access

no memory access

is

is

flexibility

compactness

pointers

code compact

loops

extra memory read

Instruction bits: A, R, mode

Addressing mode rule

Effective Address EA

Operand

Immediate: operand = A

Register: operand = R contents

Direct: EA = A

Indirect: EA = M of A

Displacement: EA = A + R

PC-relative: EA = PC + A

Auto inc/dec: EA = R, adjust R

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, addressing mode ka matlab hai: CPU ko kaise pata chalega ki operand (jis number pe kaam karna hai) actually kahan pada hai? Instruction sirf kuch bits ka hota hai, lekin memory bahut badi hoti hai. To har mode ek alag "recipe" hai jo un bits ko real jagah me convert karta hai. Sabse important cheez jo yaad rakhni hai — har mode basically Effective Address (EA) ka ek formula hai, aur jitni baar M[]M[\cdot] likhna pade utni memory access lagti hai.

Kuch modes simple: Immediate matlab value instruction ke andar hi likhi hai (zero memory access, sabse fast). Direct matlab address field hi actual address hai. Indirect thoda mehnga — pehle pointer padho, phir uss pointer wali jagah se data padho (do access lagte hain). Register indirect me pointer register me hota hai, to ek hi access. Aur Displacement (EA=A+(R)EA = A + (R)) sabse zyada use hone wala hai — R me array/struct/stack ka base hota hai aur A chhota offset. Jab bhi array[i] ya struct ka field access karte ho, andar yahi mode chal raha hota hai.

PC-relative ek smart trick hai: branch me actual address store nahi karte, balki "yahan se itne kadam aage jao" store karte hain (EA=PC+AEA = PC + A). Isse code position-independent ho jaata hai — OS program ko kahin bhi load kare, sahi chalega. Aur auto-increment/decrement stack ke push/pop aur array streaming ke liye perfect hain, kyunki pointer khud aage-piche ho jaata hai.

Exam aur interview ke liye 80/20 funda: sirf register mode (fastest) aur displacement mode achhe se samajh lo — real programs me yahi sabse zyada aate hain. Aur ek galti se bachna: register-indirect aur memory-indirect ek jaise nahi hain — memory wale me ek extra access lagta hai. Bas EA ka formula likhna seekh lo aur arrows (memory reads) gin lo, sab clear ho jaayega.

Go deeper — visual, from zero

Test yourself — Instruction Set Architecture (ISA)

Connections