Every instruction = [opcode][operand fields...]. The CPU's decode stage slices the word at fixed bit boundaries and routes each slice to the right place (register file, ALU, sign-extender, etc.).
Let's derive the RISC-V R-type (register-register) format from requirements, not memorize it.
Requirement 1 — opcode. RISC-V uses a 7-bit primary opcode. Why 7? Because 27=128 major operation classes is plenty, and 7 leaves a clean remainder in 32 bits.
Requirement 2 — three registers. RISC-V has 32 registers, so each register number needs ⌈log232⌉=5 bits. Three of them =15 bits.
Requirement 3 — distinguish similar ops.add and sub share the same opcode class, so we need extra bits to tell them apart: a 3-bit funct3 and a 7-bit funct7.
Tally:7+5+5+5+3+7=32 bits. It fits exactly — that's the point.
Imagine a robot that only understands cards with punched holes. Each card is the same size. The first few holes tell the robot what job to do (add, jump, load). The next holes tell it which boxes (registers) or what number to use. Because the "what job" holes are always in the same spot, the robot can read super fast. Sometimes a job needs a big number and not many boxes, so we punch the holes in a slightly different pattern — but the "what job" holes never move, so the robot never gets confused.
Dekho, CPU sirf bits samajhta hai — 0 aur 1. To jab hum likhte hain add x5, x6, x7, us instruction ko ek fixed-width binary word mein pack karna padta hai. Is packing ke rules ko bolte hain instruction format. Sabse pehla aur sabse important field hota hai opcode — matlab "karna kya hai" (add karna hai, jump karna hai, load karna hai). Baaki fields batate hain "kispe karna hai" — registers ya koi number (immediate).
Ab sawaal: alag-alag instructions ki zaroorat alag hoti hai. Kisi ko 3 register chahiye, kisi ko 2 register + ek bada number. Isliye ek hi 32-bit word ko hum alag-alag tareeke se baant-te hain — yeh alag layouts hi R-type, I-type, S-type wagairah kehlate hain. Lekin trick yeh hai: opcode hamesha same jagah (last 7 bits) mein rehta hai, taaki decoder turant pehchan le ki kaun sa instruction hai aur fields kahaan hain. Yeh cheez decoding ko fast banati hai.
Field ka size nikalne ka simple formula: b=⌈log2N⌉. 32 registers ke liye log232=5 bits chahiye. Ek chhota sawaal jaroor pehchano — immediate value jo instruction mein padi hai, wo ALU tak pahunchne se pehle sign-extend ya shift ho sakti hai, to raw bits aur effective value alag ho sakti hain. Yeh ek common galti hai jismein students fas jaate hain.
Last baat — fixed-length (RISC-V, ARM, MIPS = 32 bit) decode fast karta hai kyunki har instruction same size ka hai. Variable-length (x86, 1 se 15 bytes) code chhota banata hai, memory bachata hai, par decode slow hota hai. Yeh koi "better/worse" nahi, pura ek trade-off hai — yehi exam aur interview dono mein poocha jaata hai.
