5.1.2
Intuition Ek saanss mein core ideaEk CPU sirf bits padhta hai. Toh har instruction — "in do registers ko add karo", "yahan jump karo", "yeh number load karo" — ko ek fixed-width string of 0s and 1s mein squeeze karna padta hai. Ek instruction format woh agreed-upon map hai jo CPU ko bataata hai: "bits 0–6 matlab operation, bits 7–11 matlab destination register, ..." Encoding bas us map mein actual numbers bharna hai. Decoding matlab CPU ka us map ko waapis padhna.
Definition Instruction formatEk instruction format ek machine instruction word ke andar fields ka defined layout hota hai, jo specify karta hai ki har field kitne bits occupies karta hai aur har field ka kya matlab hai. Sabse important field opcode (operation code) hota hai, jo bataata hai ki kya karna hai ; baaki sab operands hote hain (registers, immediates, memory offsets) jo bataate hain ki yeh kis par karna hai .
Har instruction = [opcode][operand fields...]. CPU ka decode stage word ko fixed bit boundaries par slice karta hai aur har slice ko sahi jagah route karta hai (register file, ALU, sign-extender, etc.).
Intuition Tension: fixed width vs. varied needsMaano instruction word 32 bits wide hai (jaise RISC-V/MIPS). Alag-alag instructions ko alag-alag cheezein chahiye hoti hain:
add x1, x2, x3 ko teen register numbers chahiye.addi x1, x2, 100 ko do registers + ek number (immediate) chahiye.jal x1, target ko ek register + ek bada jump distance chahiye.
Agar humare paas sirf EK rigid layout hoti, toh hum un registers par bits waste karte jo jump instructions use nahi karti, ya phir immediate ke liye bits khatam ho jaate. Isliye hum kai formats define karte hain jo same 32 bits ko alag-alag tarike se reuse karte hain — lekin opcode ko ek fixed position par rakhte hain taaki decode hamesha pehle use dhundh sake.
Yeh hai 80/20 : samjho kyun fields idhar-udhar jaate hain jabki opcode wahi rehta hai , aur har real ISA format padhna aasaan ho jaata hai.
Chaliye RISC-V R-type (register-register) format ko requirements se derive karte hain, ratta lagaane ki jagah.
Requirement 1 — opcode. RISC-V ek 7-bit primary opcode use karta hai. 7 kyun? Kyunki 2 7 = 128
Requirement 2 — teen registers. RISC-V mein 32 registers hain, toh har register number ke liye ⌈ log 2 32 ⌉ = 5 = 15
Requirement 3 — similar ops mein distinguish karna. add aur sub ek hi opcode class share karte hain, toh unhe alag karne ke liye extra bits chahiye: ek 3-bit funct3 aur ek 7-bit funct7.
Tally: 7 + 5 + 5 + 5 + 3 + 7 = 32 exactly fit hota hai — yahi toh point hai.
7 f u n c t 7 5 r s 2 5 r s 1 3 f u n c t 3 5 r d 7 o p co d e
Definition Fixed vs. variable length
Fixed-length : har instruction same number of bits ka hota hai (RISC-V, MIPS, ARM = 32 bits). Simple, fast decoding ; kuch bits waste hoti hain.Variable-length : instructions 1 se 15 bytes tak ho sakte hain (x86). Dense code , lekin decoding slow hoti hai kyunki CPU ko pehle yeh figure out karna padta hai ki har instruction kahan khatam hoti hai .
Intuition Trade-off, explained
WHY fixed se hardware ko faayda: fetch unit hamesha exactly 4 bytes lete hai aur hamesha jaanta hai ki opcode same jagah hai → decode parallel aur pipelined ho sakta hai. Sasta, tez.WHY variable se memory bachti hai: chhoti common operations 4 ki jagah 1 byte use karti hain → programs chhote hote hain → instruction-cache hit rate behtar hoti hai.Variable ka cost yeh hai ki aap instruction n + 1 n length na pata ho → serial bottleneck.
Format
Kis liye use hota hai
Special feature
R reg-reg (add, sub)
3 registers, funct7+funct3
I immediates aur loads (addi, lw)
12-bit immediate, rs2+funct7 ki jagah
S stores (sw)
immediate do fields mein split
B branches (beq)
immediate split + cheap sign-extend ke liye reordered
U upper immediate (lui)
20-bit immediate
J jumps (jal)
20-bit immediate
split KYUN hote hain (S aur B types)
R vs. I dekho: woh opcode/rd/funct3/rs1 ko same bit positions par share karte hain. Stores ke liye humein abhi bhi rs1 aur rs2 apni usual jagah chahiye, toh 12-bit immediate ek block mein nahi baith sakta — yeh bache hue holes mein kaata jaata hai. Hardware benefit: rs1 aur rs2 kabhi nahi hilte , toh register-read logic har format ke liye identical rehta hai. Sirf immediate-assembly wiring badlati hai.
Worked example Example 1 —add x5, x6, x7 encode karo (R-type)
Fields: opcode=0110011, funct3=000, funct7=0000000, rd=5, rs1=6, rs2=7.
Yeh step kyun? Register numbers ko 5-bit binary mein convert karo: 5 = 00101 6 = 00110 7 = 00111 Kyunki har register field 5 bits wide hai. Order funct7 rs2 rs1 funct3 rd opcode mein assemble karo:
0000000 00111 00110 000 00101 0110011
Yeh order kyun? Decoder opcode lowest 7 bits mein expect karta hai aur leftward padhta hai. Fields exactly wahan rakho jahan decode dekhta hai.
Common mistake "Zyaada opcode bits ka matlab hamesha zyaada instructions available hona hai."Yeh sahi kyun lagta hai: zyaada opcode bits = zyaada patterns = zyaada operations, obviously.
Flaw: woh bits same 32-bit word se churaye jaate hain. Opcode ko diya hua har bit immediates/registers se liya hua bit hai. Bahut bada opcode useful immediate ke liye jagah nahi chodta.
Fix: word ko ek fixed budget ki tarah socho. Primary opcode badhaaye bina operations expand karne ke liye funct3/funct7 sub-fields use karo.
Common mistake "Instruction mein stored immediate value wahi final value hai jo ALU use karta hai."Yeh sahi kyun lagta hai: tune addi x1,x2,5 likha, aur 5 bits mein hai, toh 5 hi use hoga.
Flaw: branches/jumps ke liye stored immediate aksar scaled (shifted) aur sign-extended hota hai, aur uske bits reordered hote hain. Raw field ≠ effective value.
Fix: hamesha poochho "kya yeh field use hone se pehle sign-extend ya shift hota hai?" B-type ke liye, immediate 2 bytes ki units mein hota hai aur bikre hue bits se reassemble hota hai.
Common mistake "Variable-length encoding bas worse hai — fixed strictly better hai."Yeh sahi kyun lagta hai: fixed decoding itna simple hota hai.
Flaw: variable encoding chhota code deta hai, jo cache behavior aur memory bandwidth improve karta hai — x86 ke liye ek real performance win.
Fix: yeh ek trade-off hai, ranking nahi. Fixed, decode speed favor karta hai; variable, code density favor karta hai.
Recall Feynman: ek 12-saal ke bachche ko samjhaoSocho ek robot hai jo sirf punched holes waale cards samajhta hai. Har card same size ka hota hai. Pehle kuch holes robot ko bataate hain ki kya kaam karna hai (add, jump, load). Agle holes bataate hain ki kaunse boxes (registers) ya kaunsa number use karna hai. Kyunki "kya kaam" waale holes hamesha same jagah hote hain, robot bahut fast padh sakta hai. Kabhi-kabhi ek kaam ko bada number chahiye aur zyaada boxes nahi, toh hum holes thoda alag pattern mein punch karte hain — lekin "kya kaam" waale holes kabhi nahi hilte, toh robot kabhi confuse nahi hota.
Mnemonic R-type ka field order yaad karo"7-5-5-3-5-7" ek phone number ki tarah padhta hai: funct7 · rs2 · rs1 · funct3 · rd · opcode. Sum = 32 . Do 7 s ise bookend karte hain (funct7 bahar, opcode andar), 3 beech mein chhota selector hai.
Instruction format kya hota hai? Machine instruction word ke andar fields (opcode + operands) ka defined bit-layout.
Opcode formats ke across ek fixed bit position par kyun rehta hai? Taaki decoder hamesha pehle use dhundh aur padh sake, fast/pipelined decoding enable ho.
N items index karne ke liye bits ka formula? b = ⌈ log 2 N ⌉
32 registers waale register field ke liye kitne bits? 5 bits, kyunki ⌈ log 2 32 ⌉ = 5
Fixed vs variable length: kaunsa faster decode hota hai aur kyun? Fixed — har instruction same width ka hota hai aur opcode hamesha same jagah hota hai, toh length-finding step nahi hota.
Fixed vs variable length: kaunsa denser code deta hai? Variable (jaise x86) — chhote ops kam bytes use karte hain.
S/B-type formats mein immediates split KYUN hote hain? rs1/rs2 ko fixed positions par rakhne ke liye taaki register-read wiring har format ke liye identical ho; immediate bache hue holes fill karta hai.
12-bit signed (two's-complement) immediate ka range? − 2048 + 2047
32-bit ALU use karne se pehle 12-bit immediate ke saath kya hona chahiye? 32 bits tak sign-extension (aur branches/jumps ke liye scaling).
Fixed-width ISA ke liye field width sum rule? Saare field widths ka sum exactly word size ke barabar hona chahiye (jaise 32 bits).
R-type mein funct3 aur funct7 kya karte hain? Same primary opcode share karne wale operations mein sub-select karte hain (jaise add vs sub mein distinguish karna).
