x86 architecture overview

5.1.5 · Hardware › Instruction Set Architecture (ISA)

x86 aisa kyun dikhta hai?

Yeh hume kya deta hai / kya cost karta hai:

✅ Ek single binary 40 saal ke hardware par chalti hai.
❌ Instructions variable length hoti hain (1–15 bytes), jisse decoding mushkil ho jaati hai.
❌ Register set RISC ke comparison mein chota aur irregular hai.

x86 exactly kya hai?

General-purpose registers extension ke zariye bade hue, isliye unke names layered lagte hain:

64-bit	32-bit	16-bit	8-bit (low)	Traditional role
RAX	EAX	AX	AL	Accumulator
RBX	EBX	BX	BL	Base
RCX	ECX	CX	CL	Counter (loops)
RDX	EDX	DX	DL	Data
RSP	ESP	SP	—	Stack Pointer
RBP	EBP	BP	—	Base/Frame Pointer
RSI	ESI	SI	—	Source Index
RDI	EDI	DI	—	Dest Index
R8–R15	R8D…	R8W…	R8B…	x86-64 mein add hue

Ek instruction actually kaise flow karta hai

Ek x86 instruction fields ka ek sequence hai, har ek optional hai except opcode:

$[Prefixes] \to [Opcode] \to [ModR/M] \to [SIB] \to [Displacement] \to [Immediate]$

Prefix: modifiers (operand size, REX for 64-bit/extra registers, lock, repeat).
Opcode: kya karna hai (ADD, MOV…).
ModR/M + SIB: encode karta hai kaun se registers/memory operands aur addressing mode kya hai.
Displacement / Immediate: constants jo instruction mein bake hote hain.

Segmentation aur addressing (historical fossil)

Common mistakes (steel-manned)

Feynman

Recall Ek 12-saal-ke bachche ko explain karo

Socho 1978 ka ek toy robot. Har saal company ne ek better robot becha, lekin unhone promise kiya: "tumhari sari purani cassettes abhi bhi chalegi." Toh unhone kabhi purane buttons nahi hataye, sirf naye add karte rahe. Aaj ke robot mein 40 saal ke buttons stack ho gaye hain — powerful, lekin control panel thoda messy hai. Yahi hai x86: super compatible, thoda cluttered, aur abhi bhi strong chal raha hai.

Recall

Flashcards

x86 kis ISA design philosophy se belong karta hai?

CISC (Complex Instruction Set Computer)

Poori x86 family ka defining design constraint kya hai?

Intel 8086 ke saath backward compatibility

Ek x86 instruction kitni lambi ho sakti hai?

Variable length, 1 se 15 bytes tak

Real-mode physical address ka formula?

(Segment × 16) + Offset = (Segment << 4) + Offset

Segment ko 16 se multiply kyun karte hain?

16-bit segment ko 4 bits left shift karne ke liye, jo 16-bit offset ke saath 20-bit (1 MB) address span karta hai

EAX ka RAX se kya relation hai?

EAX 64-bit RAX register ke low 32 bits hai

AL ka AX se kya relation hai?

AL 16-bit AX register ke low 8 bits hai

64-bit x86 kisne introduce ki aur ise kya kehte hain?

AMD ne, 2003 mein; AMD64 / x86-64 kehte hain

8 legacy general-purpose 64-bit registers ke naam batao.

RAX, RBX, RCX, RDX, RSP, RBP, RSI, RDI

REX prefix kya enable karta hai?

64-bit operand size aur extra registers R8–R15 ka access

Ek modern x86 CPU internally CISC instruction ke saath kya karta hai?

Ise RISC-like micro-ops (µops) mein decode karta hai jo out-of-order execute hote hain

Variable-length encoding costly kyun hai?

Tum instruction n+1 locate nahi kar sakte jab tak instruction n fully decode na ho jaye, jisse decoder complicated ho jaata hai

Fetch–execute ke chaar stages?

Fetch, Decode, Execute, Write-back

64-bit (long) mode mein segmentation ka kya hua?

Mostly disabled — flat memory model use hota hai, though segment registers abhi bhi exist karte hain

Connections

RISC vs CISC — philosophical contrast; RISC fixed-length instructions kyun use karta hai
Instruction Set Architecture (ISA) — parent concept jiska x86 ek instance hai
Fetch-Decode-Execute Cycle — woh loop jisse har x86 instruction guzarti hai
Memory Addressing Modes — ModR/M aur SIB bytes inhe encode karte hain
Micro-operations (µops) — chip ke andar CISC kaise RISC banta hai
Registers and the Register File — nested RAX/EAX/AX/AL hierarchy
ARM Architecture — compare karne ke liye dominant RISC counterpart