ARM architecture overview

Intuition Core Idea

ARM (Advanced RISC Machine) is a family of RISC-based processor architectures designed around the philosophy: "Make the common case fast, make the simple case simple." Unlike x86's sprawling instruction set (thousands of instructions, complex decoding), ARM chose simplicity + efficiency: a small set of fixed-width instructions that execute in predictable cycles. This design trades software complexity for hardware simplicity, making ARM chips power-efficient (why your phone doesn't melt) and scalable (from microcontrollers to supercomputers).

WHY does this matter? In mobile/embedded systems, power is the #1 constraint. ARM's load-store architecture means fewer transistors switching per instruction → less energy wasted. In data centers, ARM's licensing model lets companies like Amazon (Graviton) or Apple (M-series) customize chips for their exact workload.

What IS ARM? (Definition + History Context)

Historical WHY: Born 1985 at Acorn Computers (UK) for BBC Micro successors. The first ARM1 processor had only 25,000 transistors (vs Intel 80286's 134,000) but matched performance. When the lead engineer accidentally left the power supply disconnected during testing, the chip kept running on leakage current from input signals—an accidental proof of extreme efficiency that became ARM's calling card.

Core Design Principles (The "WHY" Behind Choices)

1. Load-Store Architecture

Formula Memory Access Pattern

\text{Memory} \xrightarrow{\text{LDR}} \text{Registers} \xrightarrow{\text{compute}} \text{Registers} \xrightarrow{\text{STR}} \text{Memory}

Derivation from constraint: Memory access is slow (100+ cycles to DRAM). If every arithmetic instruction could touch memory (like x86's ADD [mem], reg), the pipeline stalls constantly. ARM forces:

LDR r0, [r1]      ; Load from memory to register
ADD r0, r0, #5    ; Compute (register-only)
STR r0, [r1]      ; Store back to memory

Trade-off: More instructions for memory ops, but predictable pipeline (no surprise stalls).

WHY does this help power? Memory I/O costs 10-100× more energy than register ops. By batching memory accesses and keeping data in registers, ARM reduces energy/instruction.

2. Fixed-Width Instructions (Simplified Decode)

x86 problem: Instructions are 1-15 bytes, requiring complex decoders to figure out "where does this instruction end?"

ARM solution (ARMv7): Every instruction is exactly 32 bits. Decoder just slices instruction memory into 4-byte chunks.

\text{Program Counter (PC)} \xrightarrow{+4} \text{Next Instruction}

HOW does this speed things up?

Fetch stage: Grab4 bytes, done. No variable-length parsing.
Branch prediction: Easier—branches always target PC± (offset × 4).
Parallel decode: Superscalar ARM cores can decode multiple 32-bit instructions in parallel without ambiguity.

Worked example Instruction Format (ARMv7 Data Processing)

 31-28   27-26  25  24-21  20  19-16  15-12  11-0
| Cond | 00 | I | Opcode| S |  Rn  |  Rd  | Operand2 |

Cond (4 bits): Condition code (EQ, NE, GT, etc.)—execute only if flags match.
Opcode (4 bits): Operation (ADD, SUB, MOV, etc.).
Rn, Rd: Source/destination registers (4 bits each → 16 registers).
Operand2: Immediate value or shifted register. Why this layout? Fixed fields mean hardware can decode in parallel: condition checker reads bits 31-28 while ALU control reads bits 24-21. x86 must decode serially (first byte tells how to interpret next bytes).

3. Conditional Execution (Fewer Branches)

Problem: Branches are expensive (pipeline flush if mispredicted).

ARM trick: Almost every instruction has a 4-bit condition field.

CMP r0, #0       ; Compare r0 to 0, set flags
ADDGT r1, r1, #1 ; Add 1 to r1 ONLY if r0 > 0 (Greater Than)
MOVLE r2, #0     ; Move 0 to r2 ONLY if r0 ≤ 0 (Less/Equal)

Derivation of benefit:

Without conditional execution (x86 style):
```
CMP r0, #0
JLE skip        ; Branch (pipeline hazard!)
ADD r1, r1, #1
skip: MOV r2, #0
```
If branch mispredicted: flush 10-20 instructions in pipeline (~40-80 cycles wasted on modern CPUs).
With conditional execution:
```
CMP r0, #0
ADDGT r1, r1, #1  ; Executes or becomes NOP
MOVLE r2, #0      ; Executes or becomes NOP
```
No branch → no pipeline flush. Instructions become NOPs if condition fails (1 cycle vs 40).

\text{Cycles saved} = P_{\text{mispredict}} \times C_{\text{flush}} \approx 0.15 \times 40 = 6 \text{ cycles/branch}

ARM Register Model (ARMv7 vs ARMv8)

ARMv7 (32-bit)

WHY 16 registers? Trade-off:

More registers → fewer memory accesses (good).
More registers → longer instruction encoding for register fields (bad).
16 = $2^4$ → 4 bits per register field → fits nicely in 32-bit instruction.

ARMv8 (64-bit, aka AArch64)

Backward compatibility broken (clean slate design).

WHY drop conditional execution? Modern CPUs have excellent branch predictors (>95% accuracy). Conditional execution complicates out-of-order execution (instructions don't know if they'll execute until late in pipeline). Trade-off: simpler hardware, rely on prediction.

Thumb Mode (Code Density)

Problem: 32-bit instructions waste memory when many ops are simple (e.g., MOV r0, #1).

Solution: Thumb encodes common instructions 16 bits.

Worked example Thumb Instruction

; ARM (32-bit):  0xE3A001  MOV r0, #1
; Thumb (16-bit): 0x2001      MOVS r0, #1

Restrictions in Thumb:

Only r0-r7 accessible (3-bit register fields).
No conditional execution (except IT blocks in Thumb-2).
Limited immediate values.

Thumb-2 (ARMv7): Mix of 16-bit and 32-bit instructions (e.g., ADD r0, r1, r2 is 16-bit; ADD r0, r1, #1000 is 32-bit).

WHY does this matter?

\text{Code size reduction} \approx 30\% \quad(\text{vs pure 32-bit ARM})

Smaller code → better instruction cache hit rate → faster execution + lower power (fetching from DRAM costs energy).

ARM Execution Modes (Privilege Levels)

ARMv8 Privilege Levels (simpler):

EL0: User space.
EL1: OS kernel.
EL2: Hypervisor (for virtualization).
EL3: Secure monitor (ARM TrustZone).

Pipeline Stages (Classic ARM7 Example)

3-stage pipeline (original ARM7):

Cycle 1: | Fetch    | Decode   | Execute |
Cycle 2:            | Fetch    | Decode   | Execute |
Cycle 3:                       | Fetch    | Decode   | Execute |

WHY only 3 stages? Simpler → lower latency per instruction → better for real-time embedded systems.

Modern ARM Cortex-A (ARMv7/v8): 8-15 stage pipelines (more stages → higher clock speed, but worse branch penalty).

Worked example Pipeline Hazard

LDR r0, [r1]    ; Load takes 2 cycles
ADD r2, r0, #5  ; Needs r0—must wait!

Stall: ADD waits 1 cycle (load-use hazard). ARM partially mitigates with forwarding (pass result directly from memory stage to ALU).

Common Instructions (with Derivation)

ADD (with Barrel Shifter)

ADD r0, r1, r2, LSL #2

WHAT does this do?

r0 = r1 + (r2 \ll 2) = r1 + 4 \times r2

HOW? ARM's barrel shifter is a combinational circuit that shifts operand2 for free (no extra cycle).

WHY? Array indexing:

int arr[100];
int x = arr[i];  // Address = base + i*4 (4 bytes/int)

Compiles to:

ADD r0, base, r1, LSL #2  ; r0 = base + i*4 (one instruction!)
LDR r2, [r0]

x86 needs:

LEA rax, [base + rsi*4]  ; Complex addressing mode (slower)
MOV edx, [rax]

LDM/STM (Load/Store Multiple)

LDMIA r0!, {r1-r4}  ; Load 4 words from [r0], increment r0

r1 \gets \text{Mem}[r0], \quad r2 \gets \text{Mem}[r0+4], \quad r3 \gets \text{Mem}[r0+8], \quad r4 \gets \text{Mem}[r0+12], \quad r0 \gets r0 + 16

WHY? Function prologue/epilogue:

PUSH {r4-r11, lr}  ; Save 9 registers (one instruction vs 9stores)
POP  {r4-r11, pc}  ; Restore + return (pc = lr)

Efficiency: Amortizes memory latency (one burst transaction vs9 separate accesses).

Recall Explain to a 12-Year-Old

Imagine you're organizing a school event. You have two approaches: x86 way: You have a giant rulebook with instructions for every possible situation (what if it rains? What if someone brings a dog? What if..). The rulebook is 500 pages, so finding the right rule takes forever, but once you do, it's very specific.

ARM way: You have a small manual with 20 basic rules: "Move chairs," "Count people," "Check weather." For complex tasks, you combine simple rules. Finding rules is instant (small book), but you need more steps for complicated stuff.

Why ARM? The small manual fits in your backpack (low power), and for most school events (everyday phone tasks), you don't need the 500-page rulebook. ARM trades "doing everything in one step" for "doing simple things really fast."

Connections

5.1.01-RISC-vs-CISC: ARM's philosophical foundation (why simplicity wins).
5.1.07-ARM-instruction-encoding: Bit-level breakdown of how instructions are structured.
5.2.03-pipelining: How ARM's fixed-width instructions enable efficient pipelines.
6.3.02-cache-memory: Why ARM's smaller code size (Thumb) improves cache hit rates.
7.1.05-power-optimization: ARM's dynamic voltage/frequency scaling (why phones don't overheat).
5.1.10-x86-architecture: Contrast with ARM's opposite design philosophy.

#flashcards/hardware

What is ARM's load-store architecture? :: Only LDR/STR instructions access memory; all computation happens in registers (separates memory I/O from arithmetic).

Why are ARM instructions 32 bits (ARMv7)?

Fixed width simplifies decode stage (no variable-length parsing like x86), enables parallel instruction fetch, and makes branch targets predictable (PC + 4).

What is the benefit of ARM's conditional execution?

Most instructions can execute conditionally (e.g., ADDGT), reducing branches. Fewer branches → fewer pipeline flushes from mispredictions → faster code.

How many general-purpose registers in ARMv7?

16 total: r0-r12(general), r13 (SP), r14 (LR), r15 (PC). 16 = 2^4 allows 4-bit register fields instructions.

What is Thumb mode?

16-bit instruction encoding for common operations (vs 32-bit ARM). Reduces code size by ~30%, improving instruction cache efficiency. Thumb-2 mixes 16-bit and 32-bit.

What does the barrel shifter do?

Shifts/rotates operand2 in the same cycle as the ALU operation (e.g., ADD r0, r1, r2, LSL #2). Enables efficient array indexing (address = base + index × size) in one instruction.

ARMv7 vs ARMv8 register count?

ARMv7(32-bit): 16 registers (r0-r15). ARMv8 (64-bit): 31 registers (x0-x30) + zero register (x31). More registers → fewer memory accesses.

Why did ARM drop conditional execution inMv8?

Modern branch predictors are >95% accurate, making conditional execution less valuable. Simplifies out-of-order execution logic in complex cores.

What is ARM's licensing model?

ARM designs the ISA and licenses it. Architectural license (design your own CPU, e.g., Apple). IP license (use ARM's cores, e.g., Cortex-A). This is why "ARM" chips vary widely in performance.

LDM instruction purpose?

Load Multiple registers in one instruction (e.g., LDMIA r0!, {r1-r4}). Efficient for function prologue/epilogue (save/restore multiple registers with one memory burst).

Meta Note: This note is self-contained for overview. For instruction encoding details, see 5.1.07-ARM-instruction-encoding. For pipeline hazards, see 5.2.03-pipelining. For performance tuning, see 7.1.05-power-optimization.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

ARM architecture ko samajhne ke liye ek simple analogy use karte hain. Socho ek factory hai jahan machines kaam karti hain. x86 architecture ek complicated machine hai jo bahut sare kaam ek sath kar sakti hai—lekin usko chalane ke liye bahut zyada electricity aur cooling chahiye, aur instruction manual itni badi hai ki samajhne mein time lagta hai. ARM ne kaha: "Chalo simple machines banate hain joek specific kaam efficiently kare." Jaise ek Swiss Army knife ke bajaye alag-alag dedicated tools ho—chhoti, efficient, aur kam power khane wali.

ARM ka main philosophy hai load-store architecture. Iska matlab hai ki data ko **pehle registers

What IS ARM? (Definition + History Context)

Core Design Principles (The "WHY" Behind Choices)

1. Load-Store Architecture

2. Fixed-Width Instructions (Simplified Decode)

3. Conditional Execution (Fewer Branches)

ARM Register Model (ARMv7 vs ARMv8)

ARMv7 (32-bit)

ARMv8 (64-bit, aka AArch64)

Thumb Mode (Code Density)

ARM Execution Modes (Privilege Levels)

Pipeline Stages (Classic ARM7 Example)

Common Instructions (with Derivation)

ADD (with Barrel Shifter)

LDM/STM (Load/Store Multiple)

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Instruction Set Architecture (ISA)

Connections