ARM architecture overview — Hinglish notes

5.1.6 · Hardware › Instruction Set Architecture (ISA)

Intuition Core Idea

ARM (Advanced RISC Machine) ek RISC-based processor architectures ki family hai jo is philosophy ke around design ki gayi hai: "Common case ko fast banao, simple case ko simple rakho." x86 ke sprawling instruction set (hazaron instructions, complex decoding) ke opposite, ARM ne simplicity + efficiency choose ki: ek chhota sa fixed-width instructions ka set jo predictable cycles mein execute hota hai. Yeh design software complexity ko hardware simplicity ke saath trade karta hai, jo ARM chips ko power-efficient banata hai (isliye aapka phone melt nahi hota) aur scalable bhi (microcontrollers se lekar supercomputers tak).

YEH KYUN MATTER KARTA HAI? Mobile/embedded systems mein, power sabse badi #1 constraint hai. ARM ki load-store architecture ka matlab hai ki har instruction mein kam transistors switch hote hain → kam energy waste hoti hai. Data centers mein, ARM ka licensing model companies jaise Amazon (Graviton) ya Apple (M-series) ko apne exact workload ke liye chips customize karne deta hai.

ARM KYA HAI? (Definition + History Context)

Historical WHY: 1985 mein Acorn Computers (UK) mein BBC Micro successors ke liye janam hua. Pehle ARM1 processor mein sirf 25,000 transistors the (Intel 80286 ke 134,000 ke comparison mein) lekin performance match karta tha. Jab lead engineer accidentally testing ke dauran power supply disconnected chhor gaya, toh chip input signals se leakage current par chalti rahi — extreme efficiency ka ek accidental proof jo ARM ki calling card ban gayi.

Core Design Principles (Choices ke Peeche ka "WHY")

1. Load-Store Architecture

Formula Memory Access Pattern

Memory LDR Registers compute Registers STR Memory

Constraint se derivation: Memory access slow hota hai (DRAM tak 100+ cycles). Agar har arithmetic instruction memory touch kar sakti (jaise x86 ki ADD [mem], reg), toh pipeline constantly stall hoti. ARM force karta hai:

LDR r0, [r1]      ; Load from memory to register
ADD r0, r0, #5    ; Compute (register-only)
STR r0, [r1]      ; Store back to memory

Trade-off: Memory ops ke liye zyaada instructions, lekin predictable pipeline (koi surprise stalls nahi).

YEH POWER MEIN KYUN HELP KARTA HAI? Memory I/O register ops se 10-100× zyaada energy consume karta hai. Memory accesses ko batch karke aur data ko registers mein rakhke, ARM energy/instruction reduce karta hai.

2. Fixed-Width Instructions (Simplified Decode)

x86 problem: Instructions 1-15 bytes ki hoti hain, jisme complex decoders chahiye hote hain yeh figure out karne ke liye ki "yeh instruction kahan khatam hoti hai?"

ARM solution (ARMv7): Har instruction exactly 32 bits ki hai. Decoder bas instruction memory ko 4-byte chunks mein slice karta hai.

Program Counter (PC) + 4 Next Instruction

YEH CHEEZEIN KYUN SPEED UP HOTI HAIN?

Fetch stage: 4 bytes grab karo, done. Koi variable-length parsing nahi.
Branch prediction: Aasaan hai — branches hamesha PC ± (offset × 4) ko target karte hain.
Parallel decode: Superscalar ARM cores multiple 32-bit instructions ko bina kisi ambiguity ke parallel mein decode kar sakte hain.

Worked example Instruction Format (ARMv7 Data Processing)

 31-28   27-26  25  24-21  20  19-16  15-12  11-0
| Cond | 00 | I | Opcode| S |  Rn  |  Rd  | Operand2 |

Cond (4 bits): Condition code (EQ, NE, GT, etc.) — sirf tab execute hoga jab flags match karein.
Opcode (4 bits): Operation (ADD, SUB, MOV, etc.).
Rn, Rd: Source/destination registers (4 bits each → 16 registers).
Operand2: Immediate value ya shifted register. YEH LAYOUT KYUN? Fixed fields ka matlab hai ki hardware parallel mein decode kar sakta hai: condition checker bits 31-28 read karta hai jabki ALU control bits 24-21 read karta hai. x86 ko serially decode karna padta hai (pehla byte batata hai ki agle bytes ko kaise interpret karein).

3. Conditional Execution (Fewer Branches)

Problem: Branches expensive hote hain (pipeline flush agar mispredicted ho).

ARM trick: Lagbhag har instruction mein ek 4-bit condition field hota hai.

CMP r0, #0       ; Compare r0 to 0, set flags
ADDGT r1, r1, #1 ; Add 1 to r1 ONLY if r0 > 0 (Greater Than)
MOVLE r2, #0     ; Move 0 to r2 ONLY if r0 ≤ 0 (Less/Equal)

Benefit ki derivation:

Conditional execution ke bina (x86 style):
```
CMP r0, #0
JLE skip        ; Branch (pipeline hazard!)
ADD r1, r1, #1
skip: MOV r2, #0
```
Agar branch mispredicted hua: 10-20 instructions flush pipeline mein (~40-80 cycles waste modern CPUs par).
Conditional execution ke saath:
```
CMP r0, #0
ADDGT r1, r1, #1  ; Executes or becomes NOP
MOVLE r2, #0      ; Executes or becomes NOP
```
Koi branch nahi → koi pipeline flush nahi. Agar condition fail ho toh instructions NOP ban jaate hain (1 cycle vs 40).

Cycles saved = P_{mispredict} \times C_{flush} \approx 0.15 \times 40 = 6 cycles/branch

ARM Register Model (ARMv7 vs ARMv8)

ARMv7 (32-bit)

16 REGISTERS KYUN? Trade-off:

Zyaada registers → kam memory accesses (good).
Zyaada registers → instruction mein register fields ke liye longer encoding (bad).
16 = $2^{4}$ → 4 bits per register field → 32-bit instruction mein nicely fit hota hai.

ARMv8 (64-bit, aka AArch64)

Backward compatibility todi gayi (clean slate design).

ARMv8 MEIN CONDITIONAL EXECUTION KYUN DROP KI? Modern CPUs mein excellent branch predictors hote hain (>95% accuracy). Conditional execution out-of-order execution ko complicate karta hai (instructions ko pata nahi hota ki woh execute hongi ya nahi jab tak pipeline mein late stage na ho jaaye). Trade-off: simpler hardware, prediction par rely karo.

Thumb Mode (Code Density)

Problem: 32-bit instructions memory waste karte hain jab bohot saare ops simple hote hain (jaise MOV r0, #1).

Solution: Thumb common instructions ko 16 bits mein encode karta hai.

Worked example Thumb Instruction

; ARM (32-bit):  0xE3A001  MOV r0, #1
; Thumb (16-bit): 0x2001      MOVS r0, #1

Thumb mein Restrictions:

Sirf r0-r7 accessible (3-bit register fields).
Koi conditional execution nahi (Thumb-2 mein IT blocks ke alawa).
Limited immediate values.

Thumb-2 (ARMv7): 16-bit aur 32-bit instructions ka mix (jaise ADD r0, r1, r2 16-bit hai; ADD r0, r1, #1000 32-bit hai).

YEH KYUN MATTER KARTA HAI?

Code size reduction \approx 30% (vs pure 32-bit ARM)

Chhota code → better instruction cache hit rate → faster execution + lower power (DRAM se fetch karna energy kharta hai).

ARM Execution Modes (Privilege Levels)

ARMv8 Privilege Levels (simpler):

EL0: User space.
EL1: OS kernel.
EL2: Hypervisor (virtualization ke liye).
EL3: Secure monitor (ARM TrustZone).

Pipeline Stages (Classic ARM7 Example)

3-stage pipeline (original ARM7):

Cycle 1: | Fetch    | Decode   | Execute |
Cycle 2:            | Fetch    | Decode   | Execute |
Cycle 3:                       | Fetch    | Decode   | Execute |

SIRF 3 STAGES KYUN? Simpler → har instruction ke liye lower latency → real-time embedded systems ke liye better.

Modern ARM Cortex-A (ARMv7/v8): 8-15 stage pipelines (zyaada stages → higher clock speed, lekin worse branch penalty).

Worked example Pipeline Hazard

LDR r0, [r1]    ; Load takes 2 cycles
ADD r2, r0, #5  ; Needs r0—must wait!

Stall: ADD 1 cycle wait karta hai (load-use hazard). ARM forwarding se partially mitigate karta hai (result ko directly memory stage se ALU tak pass karo).

Common Instructions (Derivation ke saath)

ADD (with Barrel Shifter)

ADD r0, r1, r2, LSL #2

YEH KYA KARTA HAI?

r 0 = r 1 + (r 2 ≪ 2) = r 1 + 4 \times r 2

KAISE? ARM ka barrel shifter ek combinational circuit hai jo operand2 ko free mein shift karta hai (koi extra cycle nahi).

KYUN? Array indexing:

int arr[100];
int x = arr[i];  // Address = base + i*4 (4 bytes/int)

Aise compile hota hai:

ADD r0, base, r1, LSL #2  ; r0 = base + i*4 (one instruction!)
LDR r2, [r0]

x86 ko chahiye:

LEA rax, [base + rsi*4]  ; Complex addressing mode (slower)
MOV edx, [rax]

LDM/STM (Load/Store Multiple)

LDMIA r0!, {r1-r4}  ; Load 4 words from [r0], increment r0

r 1 \leftarrow Mem [r 0], r 2 \leftarrow Mem [r 0 + 4], r 3 \leftarrow Mem [r 0 + 8], r 4 \leftarrow Mem [r 0 + 12], r 0 \leftarrow r 0 + 16

KYUN? Function prologue/epilogue:

PUSH {r4-r11, lr}  ; Save 9 registers (one instruction vs 9 stores)
POP  {r4-r11, pc}  ; Restore + return (pc = lr)

Efficiency: Memory latency amortize hoti hai (ek burst transaction vs 9 alag accesses).

Recall Ek 12-Saal Ke Bacche Ko Samjhao

Socho tum ek school event organize kar rahe ho. Tumhare paas do approaches hain: x86 way: Tumhare paas ek giant rulebook hai har possible situation ke liye instructions ke saath (agar barish ho toh? Agar koi dog laaye toh? Agar...). Rulebook 500 pages ki hai, toh sahi rule dhundhne mein time lagta hai, lekin jab mil jaata hai toh bahut specific hota hai.

ARM way: Tumhare paas ek chhoti manual hai 20 basic rules ke saath: "Chairs move karo," "Log count karo," "Weather check karo." Complex tasks ke liye, tum simple rules combine karte ho. Rules dhundhna instant hai (chhoti book), lekin complicated cheezon ke liye zyaada steps lagte hain.

ARM KYUN? Chhoti manual tumhare backpack mein fit hoti hai (low power), aur zyaadatar school events (everyday phone tasks) ke liye tumhe 500-page rulebook ki zaroorat nahi. ARM "sab kuch ek step mein karna" ke badle "simple cheezein bahut fast karna" trade karta hai.

Connections

5.1.01-RISC-vs-CISC: ARM ka philosophical foundation (kyun simplicity jeetti hai).
5.1.07-ARM-instruction-encoding: Instructions kaise structured hain uska bit-level breakdown.
5.2.03-pipelining: Kaise ARM ke fixed-width instructions efficient pipelines enable karte hain.
6.3.02-cache-memory: Kyun ARM ki chhoti code size (Thumb) cache hit rates improve karta hai.
7.1.05-power-optimization: ARM ka dynamic voltage/frequency scaling (kyun phones overheat nahi karte).
5.1.10-x86-architecture: ARM ke opposite design philosophy ke saath contrast.

#flashcards/hardware

ARM ki load-store architecture kya hai? :: Sirf LDR/STR instructions memory access karte hain; saari computation registers mein hoti hai (memory I/O ko arithmetic se alag karta hai).

ARM instructions 32 bits kyun hote hain (ARMv7)?

Fixed width decode stage ko simplify karta hai (x86 jaisi koi variable-length parsing nahi), parallel instruction fetch enable karta hai, aur branch targets predictable banata hai (PC + 4).

ARM ke conditional execution ka kya faayda hai?

Zyaadatar instructions conditionally execute ho sakti hain (jaise ADDGT), jo branches reduce karta hai. Kam branches → mispredictions se kam pipeline flushes → faster code.

ARMv7 mein kitne general-purpose registers hain?

16 total: r0-r12 (general), r13 (SP), r14 (LR), r15 (PC). 16 = 2^4 jo instructions mein 4-bit register fields allow karta hai.

Thumb mode kya hai?

Common operations ke liye 16-bit instruction encoding (32-bit ARM ke bajaaye). Code size ~30% reduce karta hai, instruction cache efficiency improve karta hai. Thumb-2 16-bit aur 32-bit mix karta hai.

Barrel shifter kya karta hai?

ALU operation ke saath same cycle mein operand2 ko shift/rotate karta hai (jaise ADD r0, r1, r2, LSL #2). Efficient array indexing enable karta hai (address = base + index × size) ek instruction mein.

ARMv7 vs ARMv8 register count?

ARMv7 (32-bit): 16 registers (r0-r15). ARMv8 (64-bit): 31 registers (x0-x30) + zero register (x31). Zyaada registers → kam memory accesses.

ARMv8 mein conditional execution kyun drop ki gayi?

Modern branch predictors >95% accurate hote hain, jo conditional execution ko kam valuable banata hai. Complex cores mein out-of-order execution logic simplify karta hai.

ARM ka licensing model kya hai?

ARM ISA design karta hai aur use license karta hai. Architectural license (apna khud ka CPU design karo, jaise Apple). IP license (ARM ke cores use karo, jaise Cortex-A). Isliye "ARM" chips performance mein bahut zyaada vary karte hain.

LDM instruction ka purpose kya hai?

Ek instruction mein Multiple registers load karo (jaise LDMIA r0!, {r1-r4}). Function prologue/epilogue ke liye efficient hai (ek memory burst ke saath multiple registers save/restore karo).

Meta Note: Yeh note overview ke liye self-contained hai. Instruction encoding details ke liye, dekho 5.1.07-ARM-instruction-encoding. Pipeline hazards ke liye, dekho 5.2.03-pipelining. Performance tuning ke liye, dekho 7.1.05-power-optimization.