Foundations — ARM architecture overview
Before you can understand why ARM makes the choices it makes, you need to know what every word on the parent page actually is. This page builds each one from nothing — plain words first, then a picture, then the reason ARM needs it. Read top to bottom; each idea is a brick for the next.
This is the foundation note for ARM architecture overview. Prefer to read it in Hindi-English first? See 5.1.06 ARM architecture overview (Hinglish).
1. The bit — the smallest possible fact
Picture it. Draw one switch. It is either down (0) or up (1). That's the whole universe of a bit.
Why the topic needs it. Everything ARM does — instructions, register contents, memory — is ultimately just rows of these switches. When the parent note says "32-bit instruction," it literally means a row of 32 switches.
2. Grouping bits — nibble, byte, word
Look at the figure. The bottom strip is 8 switches = one byte. Four of them stacked = 32 switches = one word. That stack of 32 is the exact size of one ARM instruction.
3. Hexadecimal — a shorthand for bits
Why it exists. Writing 1110 0011 1010 0000 is error-prone. One hex digit = one nibble, so 0xE3A0 is the same thing, four times shorter. When the parent note writes 0x2001 for a Thumb instruction, it just means "these 16 switches, grouped 4 at a time."
4. The register — a tiny named box inside the CPU
Look at the figure. On the left is the CPU with 16 labelled cubbyholes (r0–r15) — these are registers, close and instant. On the right is the huge memory wall, far away. The parent note's phrase "large register file" just means "many of these cubbyholes."
Why the topic needs it. ARM is a load-store machine: all the actual arithmetic happens between these cubbyholes. So you must picture registers as the workbench where all work is done.
5. Memory and the address — the numbered wall
Picture it. A street of identical houses. Every house holds one byte; every house has a unique number. The register r1 might hold the number 1000, meaning "go to house #1000." Notation [r1] means "the memory box whose address is inside r1" — the square brackets mean "go to the address stored here."
Why registers ≠ memory. Registers are a handful of boxes right on the desk (1 cycle to reach). Memory is a warehouse across town (100+ cycles). This distance is the entire reason ARM separates them.
6. The instruction — one order
An instruction has a mnemonic (a short human name) and often operands (what it acts on):
ADD r0, r1, r2 ; ADD is the mnemonic; r0,r1,r2 are operandsMeaning: "put r1 + r2 into r0." The word mnemonic just means "a memory-aid name" — humans write ADD, the machine stores the matching 32-bit pattern.
The details of which bits mean what are covered in 5.1.07-ARM-instruction-encoding. Here we only need to know an instruction is a fixed row of 32 switches.
7. The Program Counter (PC) and +4
Why +4? Each ARMv7 instruction is 4 bytes wide. After grabbing one, the finger must slide to the next, so:
The parent note's arrow is exactly this: because every instruction is the same 4-byte size, "next" is always "+4," no parsing needed. (Thumb instructions are 2 bytes, so there it's +2.)
8. Flags and the status register (N, Z, C, V)
Look at the figure. A CMP r0, #0 (compare r0 with zero) subtracts and throws away the answer, keeping only the flags. If r0 was 0, the Z flag lights up. If it was negative, the N flag lights up.
Why the topic needs it. Conditional execution on the parent page (ADDGT, MOVLE) is just the CPU peeking at these flags and deciding whether to run the instruction. No flags → no conditional execution. Every quadrant of comparison is covered by combinations:
Comparison of r0 to 0 |
Flags set | Conditions that fire |
|---|---|---|
r0 positive |
none / C | GT, GE, NE |
r0 = 0 |
Z | EQ, GE, LE |
r0 negative |
N | LT, LE, NE |
Recall What does
Z being 1 tell you?
The last result was exactly zero — often used to test equality after CMP.
9. Immediate values and the # sign
Why the limit matters. Because the whole instruction is only 32 bits and most bits are used for the opcode and registers, only a few bits remain for the immediate. So you can't store any number — only ones that fit. This is why Thumb has "limited immediate values" on the parent page: fewer bits left over.
10. The pipeline — an assembly line for instructions
Look at the figure. Three instructions ride the belt. At any moment one is being fetched, one decoded, one executed. The CPU finishes roughly one instruction per cycle even though each takes 3 cycles to travel the belt.
Why the topic needs it. Almost every ARM design choice is really "make the pipeline flow smoothly":
- Fixed-width instructions → easy Fetch.
- Load-store → predictable Execute timing (no surprise memory stall).
- Conditional execution → avoid flushing the belt on a branch.
A branch is an instruction that jumps the PC somewhere else. A flush is throwing away the half-done instructions on the belt because the CPU guessed the wrong next address. Deeper mechanics live in 5.2.03-pipelining.
11. RISC vs CISC — the philosophy word
The trade in one line: RISC makes the hardware simple and lets software do more small steps; CISC makes the hardware complex to keep programs short. ARM bet on simple hardware — which is why it sips power, feeding directly into power optimization.
How these foundations feed the topic
Every arrow means "you need the left idea before the right one makes sense." Trace from any leaf and you land on ARM.
Equipment checklist
Test yourself — cover the right side and answer aloud.
What is a bit, physically?
How many bits in an ARMv7 word, and how many patterns?
Why does 16 registers "fit nicely" in a 32-bit instruction?
What does one hex digit represent?
0x2001 is a compact way to write 16 switches.Difference between r1 and [r1]?
r1 is the value in the register; [r1] is the memory box at the address that value points to.